SV之testbench概述-CSDN博客

本文链接：https://blog.csdn.net/bleauchat/article/details/90552175

What is the purpose of a testbench ?

testbench允许我们通过仿真来验证设计的功能，它包括了设计以及驱动设计的激励.

（1）产生不同类型的输入激励；

（2）利用产生的激励驱动设计；

（3）设计处理输入产生输出；

（4）对比设计的输出与期望的输出；

（5）如果发现功能bug则修改设计以修复bug；

Components of a testbench

一个简单的testbench由以上几部分组成，下面详细介绍.

What is DUT ?

DUT（design under test）是由verilog或VHDL描述的硬件设计.

// All verification components are placed in this top testbench module
module tb_top;
 
  // Declare variables that need to be connected to the design instance
  // These variables are assigned some values that in turn gets transferred to
  // the design as inputs because they are connected with the ports in the design
  reg clk;        
  wire en;     
  wire wr;
  wire data;
 
  // Instantiate the design module and connect the variables declared above
  // with the ports in the design
  design myDsn ( .clk (clk),
                 .en  (en),
                 .wr  (wr),
                 . ...
                 .rdata);
 
  // Develop rest of the testbench and write stimulus that can be driven to the design
endmodule