[DRC UCIO-1]报错

[DRC UCIO-1] Unconstrained Logical Port: 10 out of 137 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.   To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].   NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.   Problem ports: DLO1CK_M, DLO1CK_P, DLO1C_M, DLO1C_P, DLO1D_M, DLO1D_P, DLO1E_M, DLO1E_P, DLO1F_M, and DLO1F_P. 

使用场景：8对LVDS查分输入。

 

检查代码，一开始以为是 该4个信号缺少负载，即缺少iserdes使用。

后发现是硬件提供的管脚，是N在前P在后，导致xdc中，P/N相反，没法绑定。

修改后，错误解决。