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VL25

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

//用状态机

	parameter s0=4'd0, s1=4'd1, s2=4'd2, s3=4'd3, s4=4'd4;
	parameter s5=4'd5, s6=4'd6, s7=4'd7, s8=4'd8,s9=4'd9;

	reg [3:0]state;
	reg [3:0]next_state;

	always@(posedge clk or negedge rst_n) begin
		if(~rst_n) begin
			state<=s0;
		end
		else 
			state<=next_state;
	end

	always@(*) begin
		case(state)
			s0: begin
                next_state = a?s0:s1;
           //     match=1'b0;
            end
			s1: begin
                next_state = a?s2:s1;
           //     match=1'b0;
            end
			s2: begin
                next_state = a?s3:s1;
            //    match=1'b0;
            end
			s3: begin 
                next_state = a?s4:s1;
            //    match=1'b0;
            end
			s4: begin
                next_state = a?s0:s5;
            //    match=1'b0;
            end
			s5: begin
                next_state = a?s2:s6;
            //    match=1'b0;
            end
			s6: begin
                next_state = a?s2:s7;
            //    match=1'b0;
            end
			s7: begin
                next_state = a?s8:s1;
            //    match=1'b0;
            end
			s8: begin
                next_state = a?s3:s1;
            //    match = 1'b1;
            end
			default: begin
                next_state = s0;
            //    match=1'b0;
            end
		endcase
	end

    always @(posedge clk or rst_n) begin
        if(~rst_n)
            match<=1'b0;
        else
            if(state==s8)
                match<=1'b1;
            else
                match<=1'b0;
    end

  
endmodule

VL26

`timescale 1ns/1ns
module sequence_detect(
    input clk,
	input rst_n,
	input a,
	output reg match
    );

    parameter s0=4'd0, s1=4'd1, s2=4'd2, s3=4'd3, s4=4'd4;
	parameter s5=4'd5, s6=4'd6, s7=4'd7, s8=4'd8, s9=4'd9;

    reg [3:0] state;
    reg [3:0] next_state;

    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            state<=s0;
        else
            state<=next_state;
    end

    always@(*) begin
        case(state)
        s0: next_state = a?s0:s1;
        s1: next_state = a?s2:s1;
        s2: next_state = a?s3:s1;
        s3: next_state = s4;
        s4: next_state = s5;
        s5: next_state = s6;
        s6: next_state = a?s7:s1;
        s7: next_state = a?s8:s1;
        s8: next_state = a?s0:s9;
        s9: next_state = a?s0:s1;
		default: next_state = s0;
        endcase
    end

    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            match <= 1'b0;
        else begin
            if(state == s9)
                match<=1'b1;
            else
                match<=1'b0;
        end
    end


endmodule

VL27

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

	parameter s0=4'd0, s1=4'd1, s2=4'd2, s3=4'd3, s4=4'd4, s5=4'd5, s6=4'd6;
    parameter d1=4'd7, d2=4'd8, d3=4'd9, d4=4'd10, d5=4'd11, d6=4'd12;

    reg [3:0] state;
    reg [3:0] next_state;

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n)
            state<=s0;
        else
            state<=next_state;
    end

    always @(*) begin
        case (state)
            s0: next_state=data?d1:s1;
            s1: next_state=data?s2:d2;
            s2: next_state=data?s3:d3;
            s3: next_state=data?s4:d4;
            s4: next_state=data?d5:s5;
            s5: next_state=data?d6:s6;
            s6: next_state=data?d1:s1;
            d1: next_state=d2;
            d2: next_state=d3;
            d3: next_state=d4;
            d4: next_state=d5;
            d5: next_state=d6;
            d6: next_state=data?d1:s1;
            default: next_state=s0;
        endcase
    end

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n) begin
            match<=1'b0;
            not_match<=1'b0;
        end
        else begin
            if(state == s5 && ~data) begin
                match<=1'b1;
                not_match<=1'b0;
            end
            else if(state == d5) begin
                match<=1'b0;
                not_match<=1'b1;
            end
            else begin
                match<=1'b0;
                not_match<=1'b0;
            end
        end
    end

endmodule

VL28

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

	parameter s0=3'd0, s1=3'd1, s2=3'd2, s3=3'd3, s4=3'd4;
    
    reg [2:0]state;
    reg [2:0]next_state;

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n)
            state<=s0;
        else
            state<=next_state;
    end

    always @(*) begin
        if(data_valid) begin
            case(state)
            s0: next_state=data?s0:s1;
            s1: next_state=data?s2:s1;
            s2: next_state=data?s3:s1;
            s3: next_state=data?s0:s4;
            s4: next_state=data?s2:s1;
            default: next_state=s0;
            endcase
        end
        else begin
            case(state)
            s0: next_state=s0;
            s1: next_state=s1;
            s2: next_state=s2;
            s3: next_state=s3;
            s4: next_state=s4;
            default: next_state=s0;
            endcase
        end
    end

    always @(posedge clk or negedge rst_n) begin
        if(~rst_n)
            match<=1'b0;
        else begin
            if(state == s3 && ~data)
                match<=1'b1;
            else
                match<=1'b0;
        end
    end

endmodule