开机信息与log

clearhlj

已于 2022-06-30 01:40:21 修改

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分类专栏： arm linux 软件调试文章标签： linux

于 2022-06-29 01:51:05 首次发布

本文链接：https://blog.csdn.net/clearhlj/article/details/125512934

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这篇博客详细记录了Linux系统启动过程中U-Boot的加载、内核启动、设备初始化等关键步骤，包括CPU频率设置、内存检测、MMC设备检测、内核模块加载等。在启动过程中遇到了输入时钟频率超过限制的问题，并展示了内核启动后的日志信息，涉及了电源管理、时钟源、I2C设备以及各种电压域的配置。

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在这里插入图片描述

U-Boot 2010.03 (Dec 23 2014 - 19:13:57) for iTOP-4412 Android

CPU: SMDK4412-AP1.1 [e4412211]
APLL = 1000MHz, MPLL = 800MHz
ARM_CLOCK = 1000MHz
PMIC: Pls check the i2c @ pmic, id = 21,error
Board: iTOP-4412-Quad
POP type: POP for C220
DRAM: 1023 MB
MMC: max_emmc_clock:40 MHZ
Set CLK to 400 KHz
EMMC CLOCK OUTPUT:: 400KHz -[div:50]
response timeout error : 00000104 cmd 8
response timeout error : 00000104 cmd 55
max_emmc_clock:40 MHZ
Input CLK [ 50 MHz] is higher than limit [40 MHZ]
Set CLK to 40000 KHz
EMMC clock output: 40000 KHz
max_emmc_clock:40 MHZ
Input CLK [ 50 MHz] is higher than limit [40 MHZ]
Set CLK to 40000 KHz
EMMC clock output: 40000 KHz
MMC0: 3728 MB
SD sclk_mmc is 400K HZ
SD sclk_mmc is 50000K HZ
SD sclk_mmc is 50000K HZ
MMC1: 30436 MB
*** Warning - using default environment

In: serial
Out: serial
Err: serial

Checking Boot Mode … SDMMC
SYSTEM ENTER NORMAL BOOT MODE
Hit any key to stop autoboot: 0
reading kernel… 1120, 12288
MMC read: dev # 1, block # 1120, count 12288 …12288 blocks read: OK
completed
reading RFS… 13408, 2048
MMC read: dev # 1, block # 13408, count 2048 …2048 blocks read: OK
completed
Boot with zImage
Wrong Ramdisk Image Format
[err] boot_get_ramdisk

Starting kernel …

Uncompressing Linux… done, booting the kernel.
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Linux version 3.0.15 (root@cym-virtual-machine) (gcc version 4.4.1 (Sourcery G++ Lite 2009q3-67) ) #17 SMP PREEMPT Tue Mar 31 22:00:53 CST 2020
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[ 0.000000] CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] Machine: SMDK4X12
[ 0.000000] **************************
[ 0.000000] reserve_panic_dump_area!!
[ 0.000000] **************************
[ 0.000000] Memory policy: ECC disabled, Data cache writealloc
[ 0.000000] CPU EXYNOS4412 (id 0xe4412211)
[ 0.000000] S3C24XX Clocks, Copyright 2004 Simtec Electronics
[ 0.000000] s3c_register_clksrc: clock audiocdclk has no registers set
[ 0.000000] audiocdclk: no parent clock specified
[ 0.000000] s3c_register_clksrc: clock armclk has no registers set
[ 0.000000] EXYNOS4: PLL settings, A=1000000000, M=800000000, E=96000000 V=350000000
[ 0.000000] EXYNOS4: ARMCLK=1000000000, DMC=400000000, AC