计算机组成实验-第4章_ALU与ALU控制器设计实验

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date:    13:15:55 03/27/2013 
// Design Name: 
// Module Name:    alu_top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//
module alu_top(clk, switch, anode, digit_anode, segment, digit_segment, led
    );
 //variable definition: op1, op2,disp_num 
 input wire clk; 
 input wire [7:0] switch;
 output wire [3:0]anode;//开发板上的四位
 output wire [7:0]segment; 
 output wire [7:0]digit_anode;//扩展板上的八位
 output wire [7:0]digit_segment; 
 output wire [2:0] led;
 
 //reg [15:0] disp_num; 
 reg [15:0] op1, op2; 
 reg [31:0] ops;
 wire [15:0] result; 
 wire [2:0]operation;
 
 initial  begin
  op1=16'b0001_0001_0010_0010;//1122 
  op2=16'b0011_0011_0100_0100;//3344 
  ops = {op1,op2};
  //led = operation;
 end 
 assign led = operation;
 aluc_top a0(clk, switch, operation );
 display  d0(clk, result,  4'b1111,  anode,  segment);  //display result
 display32bits d1(clk,ops,digit_anode,digit_segment);
 calculate_result  c1(operation,  op1,  op2,  result);  //calculate  result 
 
 
 
endmodule 
module calculate_result (operation, op1, op2, result); 
 input wire [2:0] operation; 
 input wire [15:0] op1, op2; 
 output reg [15:0] result; 
 always @* begin 
  case (operation[2:0]) //控制操??类??   3'b010:result = op1 + op2; 
   3'b110:result = op1 - op2; 
   3'b000:result = op1 & op2; 
   3'b001:result = op1|op2; 
   3'b111:result = (op1 < op2) ? 1:0; 
   default:result =0; 
  endcase 
 end 
endmodule
module display(
 input wire        clk,
 input wire [15:0] digit,//显示的数据
 input wire [3:0] dots,
 output reg [ 3:0] node, //4个数码管的位选
 output reg [ 7:0] segment);//七段+小数点
 
 reg [4:0]  code  =  5'b0;
 reg [15:0] count = 15'b0;
 initial node = 4'b1111;
 always @(posedge clk) begin
    case ({count[15:14]})
   //与(count[1:0])的不同 起到分频的作用
        3'b00 : begin
            node <= 4'b1110; 
            code <= {~dots[0],digit[3:0]};
            end
        3'b01 : begin
            node <= 4'b1101;
            code <= {~dots[1],digit[7:4]};
            end
        3'b10 : begin
            node <= 4'b1011;
            code <= {~dots[2],digit[11:8]};
            end
        3'b11 : begin
            node <= 4'b0111;
            code <= {~dots[3],digit[15:12]};
            end  
    endcase
  
  
    case (code)
        5'b00000: segment <= 8'b11000000;
        5'b00001: segment <= 8'b11111001;
        5'b00010: segment <= 8'b10100100;
        5'b00011: segment <= 8'b10110000;
        5'b00100: segment <= 8'b10011001;
        5'b00101: segment <= 8'b10010010;
        5'b00110: segment <= 8'b10000010;
        5'b00111: segment <= 8'b11111000;
        5'b01000: segment <= 8'b10000000;
        5'b01001: segment <= 8'b10010000;
        5'b01010: segment <= 8'b10001000;
        5'b01011: segment <= 8'b10000011;
        5'b01100: segment <= 8'b11000110;
        5'b01101: segment <= 8'b10100001;
        5'b01110: segment <= 8'b10000110;
        5'b01111: segment <= 8'b10001110;
    
    5'b10000: segment <= 8'b01000000;
        5'b10001: segment <= 8'b01111001;
        5'b10010: segment <= 8'b00100100;
        5'b10011: segment <= 8'b00110000;
        5'b10100: segment <= 8'b00011001;
        5'b10101: segment <= 8'b00010010;
        5'b10110: segment <= 8'b00000010;
        5'b10111: segment <= 8'b01111000;
        5'b11000: segment <= 8'b00000000;
        5'b11001: segment <= 8'b00010000;
        5'b11010: segment <= 8'b00001000;
        5'b11011: segment <= 8'b00000011;
        5'b11100: segment <= 8'b01000110;
        5'b11101: segment <= 8'b00100001;
        5'b11110: segment <= 8'b00000110;
        5'b11111: segment <= 8'b00001110;
        default: segment <= 8'b00000000;
    endcase
    count <= count + 1;
end
endmodule


module display32bits(clk,disp_num,digit_anode,segment);
 input          clk;
 input  [31:0]  disp_num;
 output [7:0]   digit_anode;
 output [7:0]   segment;
 
 reg    [7:0]   digit_anode;
 reg    [7:0]   segment;
 reg    [12:0]  cnt=0;
 wire   [31:0]  disp_num;
 reg    [3:0]   num;
 
 always@(posedge clk)begin
  case(cnt[12:10])
   3'b000:begin
    digit_anode <= 8'b11111110;
    num <= disp_num[3:0];
    end
   3'b001:begin
     digit_anode <= 8'b11111101;
     num <= disp_num[7:4];
     end
    3'b010:begin
     digit_anode <= 8'b11111011;
    num <= disp_num[11:8];
     end
    3'b011:begin
     digit_anode <= 8'b11110111;
     num <= disp_num[15:12];
     end
    3'b100:begin
    digit_anode <= 8'b11101111;
    num <= disp_num[19:16];
    end
   3'b101:begin
     digit_anode <= 8'b11011111;
     num <= disp_num[23:20];
     end
    3'b110:begin
     digit_anode <= 8'b10111111;
    num <= disp_num[27:24];
     end
    3'b111:begin
     digit_anode <= 8'b01111111;
     num <= disp_num[31:28];
     end
  endcase
 
 case(num)
   4'b0000: segment <= 8'b11000000;
        4'b0001: segment <= 8'b11111001;
        4'b0010: segment <= 8'b10100100;
        4'b0011: segment <= 8'b10110000;
        4'b0100: segment <= 8'b10011001;
        4'b0101: segment <= 8'b10010010;
        4'b0110: segment <= 8'b10000010;
        4'b0111: segment <= 8'b11111000;
        4'b1000: segment <= 8'b10000000;
        4'b1001: segment <= 8'b10010000;
        4'b1010: segment <= 8'b10001000;
        4'b1011: segment <= 8'b10000011;
        4'b1100: segment <= 8'b11000110;
        4'b1101: segment <= 8'b10100001;
        4'b1110: segment <= 8'b10000110;
        4'b1111: segment <= 8'b10001110;
        default: segment <= 8'b11111111;
  endcase
 end
 always@(posedge clk) begin
   cnt<=cnt+1;
 end
endmodule
module aluc_top(clk, switch, operation
    );
 input wire clk; 
 input wire [7:0] switch; 
 output wire [2:0] operation; 
 reg [2:0] func; 
 assign operation = func; 
 
 always @* begin 
  case(switch[7]) 
  1'b0:begin 
   if(switch[6] == 0) 
   func = 010; 
   if(switch[6] == 1) 
   func = 110; 
  end 
  1'b1:begin 
   case(switch[3:0]) 
   4'b0000:begin 
    func = 010; 
   end 
   4'b0010:begin 
    func = 110; 
   end 
   4'b0100:begin 
    func = 000; 
   end 
   4'b0101:begin 
    func = 001; 
   end 
   4'b1010:begin 
    func = 111; 
   end 
   endcase 
  end 
  endcase 
 end
endmodule
 
 
 
NET "clk" LOC = "T9" ;
NET "anode[0]" LOC = "D14" ; 
NET "anode[1]" LOC = "G14" ; 
NET "anode[2]" LOC = "F14" ; 
NET "anode[3]" LOC = "E13" ;
NET "digit_anode[0]"  LOC = "B11"  ; 
NET "digit_anode[1]"  LOC = "A10"  ; 
NET "digit_anode[2]"  LOC = "B10"  ; 
NET "digit_anode[3]"  LOC = "A9"  ; 
NET "digit_anode[4]"  LOC = "A8"  ; 
NET "digit_anode[5]"  LOC = "B8"  ;
NET "digit_anode[6]"  LOC = "A7"  ; 
NET "digit_anode[7]"  LOC = "B7"  ;


NET "segment[0]" LOC = "E14" ; 
NET "segment[1]" LOC = "G13" ; 
NET "segment[2]" LOC = "N15" ; 
NET "segment[3]" LOC = "P15" ; 
NET "segment[4]" LOC = "R16" ; 
NET "segment[5]" LOC = "F13" ; 
NET "segment[6]" LOC = "N16" ; 
NET "segment[7]" LOC = "P16" ;
NET "digit_segment[0]"  LOC = "C8"  ; 
NET "digit_segment[1]"  LOC = "D8"  ; 
NET "digit_segment[2]"  LOC = "C9"  ; 
NET "digit_segment[3]"  LOC = "D10"  ; 
NET "digit_segment[4]"  LOC = "A3"  ; 
NET "digit_segment[5]"  LOC = "B4"  ; 
NET "digit_segment[6]"  LOC = "A4"  ; 
NET "digit_segment[7]"  LOC = "B5"  ;


NET "switch[0]"  LOC = "F12"  ;
NET "switch[1]"  LOC = "G12"  ; 
net "switch[2]"  LOC = "H14";
net "switch[3]" loc="H13";
net "switch[4]" loc="J14";
net "switch[5]" loc="J13";
net "switch[6]" loc="K14";
NET "switch[7]" LOC = "K13";
NET "led[0]" loc = "k12";
net "led[1]" loc = "p14";
net "led[2]" loc = "l12";