vhdl加法器和减法器
A Subtractor is a digital circuit which performs subtraction operation.
减法器是执行减法运算的数字电路。
半减法器 (Half Subtractor)
It is a combinational circuit that performs subtraction of two binary bits. It has two inputs (minuend and subtrahend) and two outputs Difference (D) and Borrows (Bout). We use half-subtractor to subtract the LSB of the subtrahend to the LSB of the minuend when one binary number is subtracted from another. Subtraction is done according to the rule of binary subtraction and the operations can be summarized in a truth table as,
它是执行两个二进制位相减的组合电路。 它有两个输入(最小和次要)和两个输出差( D )和借款( B out )。 当从另一个二进制数中减去一个二进制数时,我们使用半减法器将被减数的LSB减去被减数的LSB。 减法是根据二进制减法的规则进行的,运算可以总结为真值表,如下所示:
A | B | Difference (D) | Borrow (Bout) |
---|---|---|---|
0 | 0 | 0 | 0 |
0 | 1 | 1 | 1 |
1 | 0 | 1 | 0 |
1 | 1 | 0 | 0 |
一个 | 乙 | 差异(D) | 借(B 出 ) |
---|---|---|---|
0 | 0 | 0 | 0 |
0 | 1个 | 1个 | 1个 |
1个 | 0 | 1个 | 0 |
1个 | 1个 | 0 | 0 |