固定流水线和可编程流水线_什么是流水线?

固定流水线和可编程流水线

Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows storing and executing instructions in an orderly process. It is also known as pipeline processing.

流水线化是通过流水线累积来自处理器的指令的过程。 它允许在有序的过程中存储和执行指令。 这也称为流水线处理

Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from one end and exit from another end.

流水线技术是一种在执行过程中重叠多条指令的技术。 管道分为多个阶段,这些阶段相互连接以形成管状结构。 指令从一端进入,从另一端退出。

Pipelining increases the overall instruction throughput.

流水线增加了整体指令吞吐量。

In pipeline system, each segment consists of an input register followed by a combinational circuit. The register is used to hold data and combinational circuit performs operations on it. The output of combinational circuit is applied to the input register of the next segment.

在流水线系统中,每个段由一个输入寄存器和一个组合电路组成。 该寄存器用于保存数据,组合电路对其进行操作。 组合电路的输出被施加到下一段的输入寄存器。

Pipelining

Pipeline system is like the modern day assembly line setup in factories. For example in a car manufacturing industry, huge assembly lines are setup and at each point, there are robotic arms to perform a certain task, and then the car moves on ahead to the next arm.

管道系统就像现代化的工厂流水线。 例如,在汽车制造业中,建立了巨大的装配线,并且在每个点处都有机械臂来执行特定任务,然后汽车向前移动到下一个臂。

管道类型 (Types of Pipeline)

It is divided into 2 categories:

它分为2类:

  1. Arithmetic Pipeline

    算术管道

  2. Instruction Pipeline

    指令流水线

算术管道 (Arithmetic Pipeline)

Arithmetic pipelines are usually found in most of the computers. They are used for floating point operations, multiplication of fixed point numbers etc. For example: The input to the Floating Point Adder pipeline is:

算术管道通常在大多数计算机中都可以找到。 它们用于浮点运算,定点数乘法等。例如:浮点加法器管道的输入为:

X = A*2^a
Y = B*2^b

Here A and B are mantissas (significant digit of floating point numbers), while a and b are exponents.

这里A和B是尾数(浮点数的有效位数),而ab是指数。

The floating point addition and subtraction is done in 4 parts:

浮点加减法分为四个部分:

  1. Compare the exponents.

    比较指数。

  2. Align the mantissas.

    对齐尾数。

  3. Add or subtract mantissas

    加或减尾数

  4. Produce the result.

    产生结果。

Registers are used for storing the intermediate results between the above operations.

寄存器用于存储上述操作之间的中间结果。

指令流水线 (Instruction Pipeline)

In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an instruction cycle. This type of technique is used to increase the throughput of the computer system.

这样,可以通过重叠指令周期的获取解码执行阶段来执行指令流。 此类技术用于增加计算机系统的吞吐量。

An instruction pipeline reads instruction from the memory while previous instructions are being executed in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will be more efficient if the instruction cycle is divided into segments of equal duration.

指令流水线从内存中读取指令,而其他指令正在流水线的其他段中执行。 因此,我们可以同时执行多个指令。 如果将指令周期划分为相等持续时间的段,则流水线将更有效。

管道冲突 (Pipeline Conflicts)

There are some factors that cause the pipeline to deviate its normal performance. Some of these factors are given below:

有一些因素会导致管道偏离其正常性能。 其中一些因素如下:

1.时间变化 (1. Timing Variations)

All stages cannot take same amount of time. This problem generally occurs in instruction processing where different instructions have different operand requirements and thus different processing time.

所有阶段都不能花费相同的时间。 此问题通常发生在指令处理中,其中不同的指令具有不同的操作数要求,因此具有不同的处理时间。

2.数据危害 (2. Data Hazards)

When several instructions are in partial execution, and if they reference same data then the problem arises. We must ensure that next instruction does not attempt to access data before the current instruction, because this will lead to incorrect results.

当几个指令正在部分执行时,如果它们引用相同的数据,则会出现问题。 我们必须确保下一条指令不会在当前指令之前尝试访问数据,因为这将导致错误的结果。

3.分支 (3. Branching)

In order to fetch and execute the next instruction, we must know what that instruction is. If the present instruction is a conditional branch, and its result will lead us to the next instruction, then the next instruction may not be known until the current one is processed.

为了获取并执行下一条指令,我们必须知道该指令是什么。 如果当前指令是条件分支,并且其结果将导致我们转到下一条指令,那么直到当前指令被处理之前,下一条指令可能是未知的。

4.中断 (4. Interrupts)

Interrupts set unwanted instruction into the instruction stream. Interrupts effect the execution of instruction.

中断将不需要的指令设置到指令流中。 中断影响指令的执行。

5.数据依赖 (5. Data Dependency)

It arises when an instruction depends upon the result of a previous instruction but this result is not yet available.

当一条指令取决于上一条指令的结果但该结果尚不可用时,就会出现这种情况。

流水线的优势 (Advantages of Pipelining)

  1. The cycle time of the processor is reduced.

    处理器的循环时间减少了。

  2. It increases the throughput of the system

    它增加了系统的吞吐量

  3. It makes the system reliable.

    它使系统可靠。

流水线的缺点 (Disadvantages of Pipelining)

  1. The design of pipelined processor is complex and costly to manufacture.

    流水线处理器的设计复杂且制造成本高。

  2. The instruction latency is more.

    指令等待时间更长。

翻译自: https://www.studytonight.com/computer-architecture/pipelining

固定流水线和可编程流水线

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流水线除法是一种通过将除法运算划分为多个子操作,并在每个时钟周期内进行部分计算的方式,可以提高除法运算的效率。在流水线除法中,将被除数、除数和商的位数分别划分为多个段,每个段在不同的时钟周期内进行计算,最终得到除法的结果。这种方式能够实现高速的除法运算,并广泛应用于计算机领域。 FPGA(可编程逻辑门阵列)是一种集成电路器件,它具有可编程的逻辑门和可配置的存储元件,可以根据用户的需求进行自定义的电路设计和实现。FPGA广泛应用于数字电路设计、信号处理、通信系统等领域。 在FPGA中实现流水线除法有许多优势。首先,FPGA具有可编程性,可以方便地进行除法计算的逻辑设计。其次,FPGA内部结构的并行处理能力使得流水线除法可以在多个时钟周期内并行运算,提高除法的计算速度。此外,FPGA的可重构性使得在设计中可以灵活地优化流水线除法的结构和功能,以达到更好的性能和资源利用率。 然而,在实现流水线除法的过程中也面临一些挑战。首先是时序约束的问题,由于流水线除法存在多个时钟周期的计算,需要特别注意时钟信号的延时和同步问题,以确保计算结果的准确性和稳定性。此外,流水线除法还需要合理划分各个子操作的计算逻辑,保证各个子段的平衡和协调,以达到最高的计算效率。 总之,流水线除法结合了流水线技术和除法运算,是一种高效的除法计算方式。在FPGA中实现流水线除法可以充分利用FPGA的可编程性、并行处理能力和可重构性,提高除法运算的效率,并适用于多种应用领域。

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