PLL Engaged External Mode (PEE)

10.4.6.2 PLL Engaged External Mode (PEE)

In this mode, the Bus clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL 
is based on the external oscillator. 
The clock sources for COP and RTI can be based on the internal reference clock generator or on the 
external oscillator clock or the RC-Oscillator (ACLK).
This mode can be entered from default mode PEI by performing the following steps:
1. Configure the PLL for desired bus frequency.
2. Enable the external oscillator (OSCE bit).
3. Wait for oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).4. Clear all flags in the CPMUFLG register to be able to detect any future status bit change.
5. Optionally status interrupts can be enabled (CPMUINT register).
Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).
The impact of loosing the oscillator status (UPOSC=0) in PEE mode is as follows:
• The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the 
PLL locks again.
• The OSCCLK provided to the MSCAN module is off.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any 
time.

 

RTIOSCSEL  :RTI Clock Select — RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the 
RTIOSCSEL bit re-starts the RTI time-out period.
RTIOSCSEL can only be set to 1, if UPOSC=1.
UPOSC= 0 clears the RTIOSCSEL bit.
0 :RTI clock source is IRCCLK.
1 :RTI clock source is OSCCLK.

 

 

Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full 
Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). In addition, the 
behavior of the COP in each mode will change based on the clocking method selected by  COPOSCSEL[1:0].
• Full Stop Mode (PSTP = 0 or OSCE=0)
External oscillator (XOSCLCP) is disabled.
— If COPOSCSEL1=0:
The COP and RTI counters halt during Full Stop Mode.
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK 
(PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0).
— If COPOSCSEL1=1:
During Full Stop Mode the COP is running on ACLK (trimmable internal RC-Oscillator clock) 
and the RTI counter halts. 
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK 
(PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0, 
RTIOSCSEL=0).