linux usb 系统 (5)

EHCI协议中规定有几种数据模型:

Periodic Frame List

Asynchronous List Queue Head Pointer

Isochronous (High-Speed) Transfer Descriptor (iTD)

Split Transaction Isochronous Transfer Descriptor (siTD)

Queue Element Transfer Descriptor (qTD)

Queue Head

Periodic Frame Span Traversal Node (FSTN)

以上数据模型(或称数据结构)就是EHCI的关键,具体的定义可以查找EHCI 的spec (Enhanced Host Controller Interface Specification for Universal Serial Bus)。EHCI控制器驱动实出上就是对这几种据结构的管理与操作。

EHCI控制器以协议的形式将这些数据模型规范下来,方案驱动设计者设计出通用的驱动,也方便非驱动设计者重用己有的驱动代码。要做到这一点,EHCI对硬件部份也需要作出一些必要的规定,这就是硬件对软件的接口--寄存器。

<>中对寄存器的序列及功能作了详细的定义,主要有以下三部份:

PCI Configuration Registers (USB)

Host Controller Capability Registers

Host Controller Operational Registers

PCI Configuration Registers的定义我们不必太关心,arm中一般不会有这一部份,我们需要详细了解的是Host Controller Capability Registers 和Host Controller Operational Registers这两大板块,

Enhanced Host Controller Capability Registers

Offset

Size

Mnemonic

Power Well

Register Name

 

00h

1

CAPLENGTH

 

Capability Register Length

 

01h

1

Reserved

 

N/A

 

02h

2

HCIVERSION

 

Interface Version Number

 

04h

4

HCSPARAMS

 

Structural Parameters

 

08h

4

HCCPARAMS

 

Capability Parameters

 

0Ch

8

HCSP-PORTROUTE

 

Companion Port Route Description

 

Host Controller Operational Registers

Offset

Mnemonic

Register Name

Power Well

  

00h

USBCMD

USB Command

   

04h

USBSTS

USB Status

   

08h

USBINTR

USB Interrupt Enable

   

0ch

FRINDEX

USB Frame Index

   

10h

CTRLDSSEGMENT

4G Segment Selector

   

14h

PERIODICLISTBASE

Frame List Base Address

   

18h

ASYNCLISTADDR

Next Asynchronous List Address

   

1C-3F

Reserved

    

40H

CONFIGFLAG

Configured Flag Register

   

44H

PORTSC(1-N_PORTS)

Port Status/Control

   

在一些主芯片的spec中,USB主控制器的部份就介绍得很简单,大多数只是像我这样简单的说一下USB主控制器的标准,再列一下寄存器的序列,然后让读者去查找<这样的文档。

上表中标成红色的寄存器是我们需要主要关注的,echi主控制器会以此为入口,对各种数据模型进行调度。

主控制器的调度主要分为两大数,一类可以称为时间片的调度,多数控制器会以此种调度为主,另一种则是异步(Asynchronous)调度。

USB协议中把USB的传输类型分为控制传输,批量传输,中断传输,等时传输。这几种传输类型的定义其实是逻辑上的。我们知道,USB的物理数据通道就一条(D+/D-),要怎样才能达到USB协议中这几种传输类型的要求呢,这就要看主控制器是如何调度的了。

在EHCI中,把等时传输和中断传输都用进间片调度来控制。请看下图:

clip_image002
所谓的分时调度,就是把每秒的时间分为若干片(一般是1024/256等),每一个时间片(Frame)处理一组(一般是ISO数据)数据。

CPU会把ISO数据和INT数据建立一张表放在内核中,而ECHI的寄存器FRINDEX则会跟踪这个表,每一个时间片加-,FRINDEX所指之处,控制器就会把这处指针所指向的数据结构中的数据送到总线上去。整个过程看起来有点像是CPU的调度。

有了时间片的调度,其实控制器就可以完成所有的功能,但为了方便用户的使用,控制器还提拱了另一种调度来处理实时性要求不是很强的数据。

clip_image004
这种调试一般叫做异步调度,也就是AsyncListAddr发威的时候了,CPU把块传输和控制传输的数据按协议要求的数据结构在内存中安排好并建立一个链表,AsyncListAddr则会跟踪这个链表,控制器则把AsyncListAddr所指向的数据搬运到USB总线上去。

异步调度比ISO调度要简单得多了。至于异步调试和同步调度之间如何协调,EHCI控制器会处理这个问题,再也不用软件来操心了。

有了以上的简章介绍,我们知道EHCI的规范中对寄存器,数据结构和控制方式都有了详细的规定,linux是怎样执行这个规定的呢。

 

注:转载请注明出处 datangsoc@hotmail.com

Enhanced Host Controller Interface Specification for Universal Serial Bus<br><br>1. INTRODUCTION...............................................................................................1 <br>1.1 EHCI Product Compliance.................................................................................................................2 <br>1.2 Architectural Overview.......................................................................................................................2 <br>1.2.1 Interface Architecture....................................................................................................................4 <br>1.2.2 EHCI Schedule Data Structures.....................................................................................................5 <br>1.2.3 Root Hub Emulation......................................................................................................................5 <br>2. REGISTER INTERFACE ..................................................................................7 <br>2.1 PCI Configuration Registers (USB)...................................................................................................8 <br>2.1.1 PWRMGT ? PCI Power Management Interface..........................................................................8 <br>2.1.2 CLASSC ? CLASS CODE REGISTER......................................................................................9 <br>2.1.3 USBBASE ? Register Space Base Address Register..................................................................9 <br>2.1.4 SBRN ? Serial Bus Release Number Register.............................................................................9 <br>2.1.5 Frame Length Adjustment Register (FLADJ)..............................................................................10 <br>2.1.6 Port Wake Capability Register (PORTWAKECAP)...................................................................11 <br>2.1.7 USBLEGSUP ? USB Legacy Support Extended Capability.....................................................11 <br>2.1.8 USBLEGCTLSTS ? USB Legacy Support Control/Status........................................................12 <br>2.2 Host Controller Capability Registers...............................................................................................13 <br>2.2.1 CAPLENGTH ? Capability Registers Length...........................................................................13 <br>2.2.2 HCIVERSION ? Host Controller Interface Version Number....................................................14 <br>2.2.3 HCSPARAMS ? Structural Parameters.....................................................................................14 <br>2.2.4 HCCPARAMS ? Capability Parameters....................................................................................15 <br>2.2.5 HCSP-PORTROUTE ? Companion Port Route Description.....................................................16 <br>2.3 Host Controller Operational Registers............................................................................................17 <br>2.3.1 USBCMD ? USB Command Register.......................................................................................18 <br>2.3.2 USBSTS ? USB Status Register................................................................................................21 <br>2.3.3 USBINTR ? USB Interrupt Enable Register..............................................................................22 <br>2.3.4 FRINDEX ? Frame Index Register............................................................................................23 <br>2.3.5 CTRLDSSEGMENT ? Control Data Structure Segment Register............................................24 <br>2.3.6 PERIODICLISTBASE ? Periodic Frame List Base Address Register......................................24 <br>2.3.7 ASYNCLISTADDR ? Current Asynchronous List Address Register.......................................25 <br>2.3.8 CONFIGFLAG ? Configure Flag Register................................................................................25 <br>2.3.9 PORTSC ? Port Status and Control Register.............................................................................26 <br>3. DATA STRUCTURES.....................................................................................31 <br>3.1 Periodic Frame List...........................................................................................................................31 <br>3.2 Asynchronous List Queue Head Pointer..........................................................................................32 <br>3.3 Isochronous (High-Speed) Transfer Descriptor (iTD)....................................................................33 <br>USB 2.0 i <br><br>EHCI Revision 1.0 3/12/2002 <br>3.3.1 Next Link Pointer.........................................................................................................................33 <br>3.3.2 iTD Transaction Status and Control List......................................................................................34 <br>3.3.3 iTD Buffer Page Pointer List (Plus).............................................................................................35 <br>3.4 Split Transaction Isochronous Transfer Descriptor (siTD)...........................................................36 <br>3.4.1 Next Link Pointer.........................................................................................................................37 <br>3.4.2 siTD Endpoint Capabilities/Characteristics.................................................................................37 <br>3.4.3 siTD Transfer State......................................................................................................................38 <br>3.4.4 siTD Buffer Pointer List (plus)....................................................................................................39 <br>3.4.5 siTD Back Link Pointer...............................................................................................................40 <br>3.5 Queue Element Transfer Descriptor (qTD).....................................................................................40 <br>3.5.1 Next qTD Pointer.........................................................................................................................41 <br>3.5.2 Alternate Next qTD Pointer.........................................................................................................41 <br>3.5.3 qTD Token...................................................................................................................................42 <br>3.5.4 qTD Buffer Page Pointer List......................................................................................................45 <br>3.6 Queue Head........................................................................................................................................46 <br>3.6.1 Queue Head Horizontal Link Pointer...........................................................................................46 <br>3.6.2 Endpoint Capabilities/Characteristics..........................................................................................47 <br>3.6.3 Transfer Overlay..........................................................................................................................49 <br>3.7 Periodic Frame Span Traversal Node (FSTN)................................................................................51 <br>3.7.1 FSTN Normal Path Pointer..........................................................................................................51 <br>3.7.2 FSTN Back Path Link Pointer......................................................................................................52 <br>4. OPERATIONAL MODEL................................................................................53 <br>4.1 Host Controller Initialization............................................................................................................53 <br>4.2 Port Routing and Control..................................................................................................................54 <br>4.2.1 Port Routing Control via EHCI Configured (CF) Bit..................................................................55 <br>4.2.2 Port Routing Control via PortOwner and Disconnect Event.......................................................56 <br>4.2.3 Example Port Routing State Machine..........................................................................................57 <br>4.2.4 Port Power....................................................................................................................................57 <br>4.2.5 Port Reporting Over-Current........................................................................................................58 <br>4.3 Suspend/Resume................................................................................................................................59 <br>4.3.1 Port Suspend/Resume..................................................................................................................59 <br>4.4 Schedule Traversal Rules..................................................................................................................61 <br>4.4.1 Example - Preserving Micro-Frame Integrity..............................................................................62 <br>4.5 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries..................................................64 <br>4.6 Periodic Schedule...............................................................................................................................66 <br>4.7 Managing Isochronous Transfers Using iTDs.................................................................................67 <br>4.7.1 Host Controller Operational Model for iTDs...............................................................................67 <br>4.7.2 Software Operational Model for iTDs.........................................................................................69 <br>4.8 Asynchronous Schedule.....................................................................................................................71 <br>4.8.1 Adding Queue Heads to Asynchronous Schedule........................................................................71 <br>4.8.2 Removing Queue Heads from Asynchronous Schedule..............................................................72 <br>4.8.3 Empty Asynchronous Schedule Detection...................................................................................74 <br>ii USB 2.0 <br><br>EHCI Revision 1.0 3/12/2002 <br>4.8.4 Restarting Asynchronous Schedule Before EOF.........................................................................74 <br>4.8.5 Asynchronous Schedule Traversal : Start Event..........................................................................76 <br>4.8.6 Reclamation Status Bit (USBSTS Register)................................................................................77 <br>4.9 Operational Model for Nak Counter................................................................................................77 <br>4.9.1 Nak Count Reload Control...........................................................................................................78 <br>4.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads....................................................79 <br>4.10.1 Fetch Queue Head........................................................................................................................80 <br>4.10.2 Advance Queue............................................................................................................................81 <br>4.10.3 Execute Transaction.....................................................................................................................81 <br>4.10.4 Write Back qTD...........................................................................................................................86 <br>4.10.5 Follow Queue Head Horizontal Pointer.......................................................................................86 <br>4.10.6 Buffer Pointer List Use for Data Streaming with qTDs...............................................................86 <br>4.10.7 Adding Interrupt Queue Heads to the Periodic Schedule.............................................................88 <br>4.10.8 Managing Transfer Complete Interrupts from Queue Heads.......................................................88 <br>4.11 Ping Control.......................................................................................................................................88 <br>4.12 Split Transactions..............................................................................................................................89 <br>4.12.1 Split Transactions for Asynchronous Transfers...........................................................................90 <br>4.12.2 Split Transaction Interrupt...........................................................................................................92 <br>4.12.3 Split Transaction Isochronous....................................................................................................103 <br>4.13 Host Controller Pause......................................................................................................................114 <br>4.14 Port Test Modes...............................................................................................................................114 <br>4.15 Interrupts..........................................................................................................................................115 <br>4.15.1 Transfer/Transaction Based Interrupts.......................................................................................115 <br>4.15.2 Host Controller Event Interrupts................................................................................................117 <br>5. EHCI EXTENDED CAPABILITIES...............................................................121 <br>5.1 EHCI Extended Capability: Pre-OS to OS Handoff Synchronization........................................121 <br>APPENDIX A. EHCI PCI POWER MANAGEMENT INTERFACE......................125 <br>A.1 PCI Power Management Register Interface..................................................................................125 <br>A.1.1 Power State Transitions.............................................................................................................126 <br>A.1.2 Power State Definitions.............................................................................................................126 <br>A.1.3 PCI PME# Signal.......................................................................................................................127 <br>APPENDIX B. EHCI 64-BIT DATA STRUCTURES............................................129 <br>APPENDIX C. DEBUG PORT.............................................................................133 <br>C.1 Locating the Debug Port..................................................................................................................133 <br>C.2 Using the Debug Port Fields............................................................................................................134 <br>C.3 USB2 Debug Port Register Interface..............................................................................................134 <br>USB 2.0 iii <br><br>EHCI Revision 1.0 3/12/2002 <br>C.3.1 Debug Port Control Register......................................................................................................135 <br>C.3.2 USB PIDs Register.....................................................................................................................137 <br>C.3.3 Data Buffer.................................................................................................................................137 <br>C.3.4 Device Address Register............................................................................................................138 <br>C.4 Operational Model...........................................................................................................................138 <br>C.4.1 OUT/SETUP Transactions.........................................................................................................139 <br>C.4.2 IN transactions...........................................................................................................................139 <br>C.4.3 Debug Software Startup.............................................................................................................139 <br>C.4.4 Finding the Debug Peripheral....................................................................................................140 <br>APPENDIX D. HIGH BANDWIDTH ISOCHRONOUS RULES............................141 <br> <br>
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