;==================================================================== ; File Name : MiniBoot.s ; Function : 初始化Mini2440开发板,使得JTAG可以调试ROM/RAM中的代码 ; 关闭看门狗,屏蔽中断和子中断,配置存储器 ; Revision : V1.0 2009-03-20 dddkkf ; Revision : V1.1 2009-03-30 dddkkf 增加异常跳转、栈初始化 ;==================================================================== ; 参考代码<2440mini.s> <2440add.inc> <memcfg.inc> ; 编译器:ADS1.2 ; 芯片类型:S32440A(ARM920T) ; 链接选项:-entry 0 -ro-base 0 -first MiniBoot.o(boot) ; 烧录到NAND Flash 地址0x0000_0000 ;==================================================================== ; File Name : 2440addr.a ; Function : S3C2440 Define Address Register (Assembly) ; Date : March 27, 2002 ; Revision : Programming start (February 18,2002) -> SOP ; Revision : 03.11.2003 ver 0.0 Attatched for 2440 ;==================================================================== ;================= ; Memory control ;================= BWSCON EQU 0x48000000 ;Bus width & wait status BANKCON0 EQU 0x48000004 ;Boot ROM control BANKCON1 EQU 0x48000008 ;BANK1 control BANKCON2 EQU 0x4800000c ;BANK2 control BANKCON3 EQU 0x48000010 ;BANK3 control BANKCON4 EQU 0x48000014 ;BANK4 control BANKCON5 EQU 0x48000018 ;BANK5 control BANKCON6 EQU 0x4800001c ;BANK6 control BANKCON7 EQU 0x48000020 ;BANK7 control REFRESH EQU 0x48000024 ;DRAM/SDRAM refresh BANKSIZE EQU 0x48000028 ;Flexible Bank Size MRSRB6 EQU 0x4800002c ;Mode register set for SDRAM Bank6 MRSRB7 EQU 0x48000030 ;Mode register set for SDRAM Bank7 ;================= ; INTERRUPT ;================= INTMSK EQU 0x4a000008 ;Interrupt mask control INTSUBMSK EQU 0x4a00001c ;Interrupt sub mask ;================= ; WATCH DOG TIMER ;================= WTCON EQU 0x53000000 ;Watch-dog timer mode ;************************************************ ; NAME : MEMCFG.A ; DESC : Memory bank configuration file ; Revision: 02.28.2002 ver 0.0 ; Revision: 03.11.2003 ver 0.0 Attatched for 2440 ;************************************************ ; SDRAM位于GCS6片选,地址为0x3000_0000-0x33ff_ffff ; 总线宽度枚举值 ;BWSCON DW16 EQU (0x1) DW32 EQU (0x2) ; 评估板的内存组总线宽度 ; 不定义B0_BWSCON,是因为BANK0作为启动ROM,在访问前必须确定总线宽度,由OM[0:1]决定 B1_BWSCON EQU (DW32) ; Intel Strata(28F128), 32-bit, for nCS1 when NOR Flash booting. B2_BWSCON EQU (DW16) ; PCMCIA(PD6710), 16-bit B3_BWSCON EQU (0xd) ; Ethernet(CS8900), 16-bit B4_BWSCON EQU (DW16) ; NOR flash(AM29LV800B), 16-bit, for nCS4 when NAND booting. B5_BWSCON EQU (DW16) ; A400/A410 Ext, 16-bit B6_BWSCON EQU (DW32) ; SDRAM(K4S561632C) 32MBx2, 32-bit B7_BWSCON EQU (DW32) ; N.C. ; Mini2440,NOR或NAND启动 ; Tacs 地址有效后,等待CS ; Tcos CS有效后,等待OE ; Tacc 访问时间 ; Tcoh OE无效后,保持CS ; Tah CS无效后,保持地址 ; Tacp Page模式下的访问时间 ; TPMC Page模式访问 ; MT 内存类型:0=SROM/3=SDRAM, ; Trcd RAS到CAS的延时(地址建立时间) ; SCAN 列地址位数(8/9/10bit) ; Trp RAS预充电时间 ; Tsrc 半行周期时间 ; Trc=Tsrc+Trp 行周期时间 ;BANK0CON B0_Tacs EQU 0x0 ;0clk B0_Tcos EQU 0x0 ;0clk B0_Tacc EQU 0x7 ;14clk B0_Tcoh EQU 0x0 ;0clk B0_Tah EQU 0x0 ;0clk B0_Tacp EQU 0x0 B0_PMC EQU 0x0 ;normal ;BANK1CON B1_Tacs EQU 0x0 ;0clk B1_Tcos EQU 0x0 ;0clk B1_Tacc EQU 0x7 ;14clk B1_Tcoh EQU 0x0 ;0clk B1_Tah EQU 0x0 ;0clk B1_Tacp EQU 0x0 B1_PMC EQU 0x0 ;normal ;Bank 2 parameter B2_Tacs EQU 0x0 ;0clk B2_Tcos EQU 0x0 ;0clk B2_Tacc EQU 0x7 ;14clk B2_Tcoh EQU 0x0 ;0clk B2_Tah EQU 0x0 ;0clk B2_Tacp EQU 0x0 B2_PMC EQU 0x0 ;normal ; Mini2440,LAN ;Bank 3 parameter B3_Tacs EQU 0x1 ;0clk B3_Tcos EQU 0x3 ;0clk B3_Tacc EQU 0x7 ;14clk B3_Tcoh EQU 0x2 ;0clk B3_Tah EQU 0x1 ;0clk B3_Tacp EQU 0x3 B3_PMC EQU 0x0 ;normal ;Bank 4 parameter B4_Tacs EQU 0x0 ;0clk B4_Tcos EQU 0x0 ;0clk B4_Tacc EQU 0x7 ;14clk B4_Tcoh EQU 0x0 ;0clk B4_Tah EQU 0x0 ;0clk B4_Tacp EQU 0x0 B4_PMC EQU 0x0 ;normal ;Bank 5 parameter B5_Tacs EQU 0x0 ;0clk B5_Tcos EQU 0x0 ;0clk B5_Tacc EQU 0x7 ;14clk B5_Tcoh EQU 0x0 ;0clk B5_Tah EQU 0x0 ;0clk B5_Tacp EQU 0x0 B5_PMC EQU 0x0 ;normal ; HY57V561620 (32MB=4Banks x 4M x 16Bit) ; Data mask function by UDQM and LDQM ; Auto refresh and self refresh, 8192 refresh cycles / 64ms ; Programmable CAS Latency ; 2, 3 Clocks ; Row Address : RA0~12, Column Address: CA0~8 ;Bank 6 parameter B6_MT EQU 0x3 ;SDRAM B6_Trcd EQU 0x2 ;4clk B6_SCAN EQU 0x1 ;9bit ;Bank 7 parameter B7_MT EQU 0x3 ;SDRAM B7_Trcd EQU 0x2 ;4clk B7_SCAN EQU 0x1 ;9bit ;REFRESH parameter REFEN EQU 0x1 ;Refresh enable TREFMD EQU 0x0 ;CBR(CAS before RAS)/Auto refresh Trp EQU 0x2 ;4clk Trc EQU 0x2 ;6clk Tchr EQU 0x2 ;3clk REFCNT EQU 1269 ;period=7.8us, HCLK=100Mhz, (2048+1-7.8*100) ;=========================================== ; NAME: OPTION.A ; DESC: Configuration options for .S files ; HISTORY: ; 02.28.2002: ver 0.0 ; 03.11.2003: ver 0.0 attached for 2440. ; jan E, 2004: ver0.03 modified for 2440A01. ;=========================================== _STACK_BASEADDRESS EQU 0x33ff8000 ; 堆栈起址 _ISR_STARTADDRESS EQU 0x33ffff00 ; ISR起址 ;------------------------------------------------------------------------------ ; 代码入口 ;------------------------------------------------------------------------------ AREA boot, CODE, READONLY ENTRY CODE32 _BootEntry b ResetHandler b HandlerUndef ;handler for Undefined mode b HandlerSWI ;handler for SWI interrupt b HandlerPabort ;handler for PAbort b HandlerDabort ;handler for DAbort b . ;reserved b HandlerIRQ ;handler for IRQ interrupt b HandlerFIQ ;handler for FIQ interrupt ResetHandler ; 关闭看门狗(默认是使用看门狗复位功能,调试模式时禁止) ; [WTCON]=0x0 ldr r0,=WTCON ;watch dog disable ldr r1,=0x0 str r1,[r0] ; 屏蔽所有32个中断(默认允许中断) ; [INTMSK]=0xffffffff ldr r0,=INTMSK ldr r1,=0xffffffff ;all interrupt disable str r1,[r0] ; 屏蔽所有15个子中断(默认允许子中断) ; [INTSUBMSK]=0x7fff ldr r0,=INTSUBMSK ldr r1,=0x7fff ;all sub interrupt disable str r1,[r0] ; 把SMRDATA内存配置信息写入BWSCON开始的13个存储器控制寄存器 ; memcpy(BWSCON, SMRDATA, 52) adr r0,SMRDATA ldr r1,=BWSCON ;BWSCON Address add r2, r0, #52 ;End address of SMRDATA 0 ldr r3, [r0], #4 str r3, [r1], #4 cmp r2, r0 bne %B0 ; 初始化各种工作模式的堆栈 bl InitStacks ; 完成初始化 b . ; 存储器配置信息 SMRDATA DATA ; 各Bank总线宽度 DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) ; SROM访问时序 DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0 DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1 DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2 DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3 DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4 DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5 ; SDRAM设置 DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6 DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7 DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M DCD 0x30 ;MRSR6 CL=3clk DCD 0x30 ;MRSR7 CL=3clk ;------------------------------------------------------------------------------ ; 栈初始化 ;------------------------------------------------------------------------------ ; ARM工作模式,与PSR定义相同 ;Pre-defined constants USERMODE EQU 0x10 FIQMODE EQU 0x11 IRQMODE EQU 0x12 SVCMODE EQU 0x13 ABORTMODE EQU 0x17 UNDEFMODE EQU 0x1b MODEMASK EQU 0x1f NOINT EQU 0xc0 ; 各种工作模式的堆栈起址,_STACK_BASEADDRESS在option.inc种定义 ;The location of stacks UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~ UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~ AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~ IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~ FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~ ; 初始化各种工作模式的堆栈 void InitStacks(); ;function initializing stacks InitStacks ;Don''t use DRAM,such as stmfd,ldmfd...... ;SVCstack is initialized before ;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1' mrs r0,cpsr bic r0,r0,#MODEMASK ; 切换到undef模式,SPund=UndefStack orr r1,r0,#UNDEFMODE|NOINT msr cpsr_cxsf,r1 ;UndefMode ldr sp,=UndefStack ; UndefStack=0x33FF_5C00 ; 切换到abt模式,SPabt=AbortStack orr r1,r0,#ABORTMODE|NOINT msr cpsr_cxsf,r1 ;AbortMode ldr sp,=AbortStack ; AbortStack=0x33FF_6000 ; 切换到irq模式,SPirq=IRQStack orr r1,r0,#IRQMODE|NOINT msr cpsr_cxsf,r1 ;IRQMode ldr sp,=IRQStack ; IRQStack=0x33FF_7000 ; 切换到fiq模式,SPfiq=FIQStack orr r1,r0,#FIQMODE|NOINT msr cpsr_cxsf,r1 ;FIQMode ldr sp,=FIQStack ; FIQStack=0x33FF_8000 ; 切换到svc模式,SPsvc=SVCStack bic r0,r0,#MODEMASK|NOINT orr r1,r0,#SVCMODE msr cpsr_cxsf,r1 ;SVCMode ldr sp,=SVCStack ; SVCStack=0x33FF_5800 ; usr模式没有被初始化,一般有C语言设置 ;USER mode has not be initialized. mov pc,lr ;The LR register won''t be valid if the current mode is not SVC mode. ;------------------------------------------------------------------------------ ; 处理异常 ;------------------------------------------------------------------------------ ; 定义处理异常向量的例程,实现远程跳转 ; 宏使用了r0寄存器,并采用满递减堆栈保存r0寄存器的初始值,并在使用后恢复。 ; 在使用ldmfd语句跳转之前,堆栈如下所示 ; sp+0 -> [IsrEntry] ; sp+4 -> r0 ; sp+8 -> 原始的堆栈 MACRO $HandlerLabel HANDLER $pISR $HandlerLabel sub sp,sp,#4 ;decrement sp(to store jump address) stmfd sp!,{r0} ;PUSH the work register to stack(lr does''t push because it return to original address) ldr r0,=$pISR;load the address of HandleXXX to r0 ldr r0,[r0] ;load the contents(service routine start address) of HandleXXX str r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stack ldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR) MEND ; 异常处理例程 LTORG HandlerFIQ HANDLER ISR_FIQ HandlerIRQ HANDLER ISR_IRQ HandlerUndef HANDLER ISR_Undef HandlerSWI HANDLER ISR_SWI HandlerDabort HANDLER ISR_Dabort HandlerPabort HANDLER ISR_Pabort ; 异常向量表 ALIGN AREA ISRTable, DATA, READWRITE MAP _ISR_STARTADDRESS ; 向量表起始地址 ISR_Reset # 4 ISR_Undef # 4 ISR_SWI # 4 ISR_Pabort # 4 ISR_Dabort # 4 ISR_Reserved # 4 ISR_IRQ # 4 ISR_FIQ # 4 END