修改.svd仿真文件

仿真寄存器描述svd文件

在用vs code做stm32f072开发时遇到了仿真文件与手册描述不一致问题，简单提供一下修改方法。

dac监控问题

stm32f072x.svd的dac描述沿用了f051的，只描述了一个dac外设。然而072具有两个dac，可以实现双路的dac输出。而仿真文件便于我们观察dac的工作状态，iar中我并没有找到相关的文件无法修改。

修改

<peripheral>
      <name>DAC</name>
      <description>Digital-to-analog converter</description>
      <groupName>DAC</groupName>
      <baseAddress>0x40007400</baseAddress>
      <addressBlock>
        <offset>0x0</offset>
        <size>0x400</size>
        <usage>registers</usage>
      </addressBlock>
      <interrupt>
        <name>TIM6_DAC_IRQ</name>
        <description>TIM6 global interrupt and DAC underrun
        interrupt</description>
        <value>17</value>
      </interrupt>
      <registers>
        <register>
          <name>CR</name>
          <displayName>CR</displayName>
          <description>control register</description>
          <addressOffset>0x0</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>EN1</name>
              <description>DAC channel1 enable</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BOFF1</name>
              <description>DAC channel1 output buffer
              disable</description>
              <bitOffset>1</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEN1</name>
              <description>DAC channel1 trigger
              enable</description>
              <bitOffset>2</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSEL10</name>
              <description>DAC channel1 trigger
              selection</description>
              <bitOffset>3</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSEL11</name>
              <description>DAC channel1 trigger
              selection</description>
              <bitOffset>4</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSEL12</name>
              <description>DAC channel1 trigger
              selection</description>
              <bitOffset>5</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAEN1</name>
              <description>DAC channel1 DMA enable</description>
              <bitOffset>12</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAUDRIE1</name>
              <description>DAC channel1 DMA Underrun Interrupt
              enable</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            

			<field>
              <name>EN2</name>
              <description>DAC channel2 enable</description>
              <bitOffset>16</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>BOFF2</name>
              <description>DAC channel2 output buffer
              disable</description>
              <bitOffset>17</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TEN2</name>
              <description>DAC channel2 trigger
              enable</description>
              <bitOffset>18</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>TSEL2</name>
              <description>DAC通道2 触发选择</description>
              <bitOffset>19</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>WAVE2</name>
              <description>DAC通道2 噪声/三角波生成启用</description>
              <bitOffset>22</bitOffset>
              <bitWidth>2</bitWidth>
            </field>
            <field>
              <name>MAMP2</name>
              <description>DAC通道2 掩模/幅度选择器</description>
              <bitOffset>24</bitOffset>
              <bitWidth>3</bitWidth>
            </field>
            <field>
              <name>DMAEN2</name>
              <description>DAC通道2 DMA使能</description>
              <bitOffset>28</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAUDRIE2</name>
              <description>DAC通道2 DMA欠载中断使能</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>


          </fields>
        </register>
        <register>
          <name>SWTRIGR</name>
          <displayName>SWTRIGR</displayName>
          <description>software trigger register</description>
          <addressOffset>0x4</addressOffset>
          <size>0x20</size>
          <access>write-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>SWTRIG1</name>
              <description>DAC channel1 software
              trigger</description>
              <bitOffset>0</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DHR12R1</name>
          <displayName>DHR12R1</displayName>
          <description>channel1 12-bit right-aligned data holding
          register</description>
          <addressOffset>0x8</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 12-bit right-aligned
              data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DHR12L1</name>
          <displayName>DHR12L1</displayName>
          <description>channel1 12-bit left aligned data holding
          register</description>
          <addressOffset>0xC</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 12-bit left-aligned
              data</description>
              <bitOffset>4</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DHR8R1</name>
          <displayName>DHR8R1</displayName>
          <description>channel1 8-bit right aligned data holding
          register</description>
          <addressOffset>0x10</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DHR</name>
              <description>DAC channel1 8-bit right-aligned
              data</description>
              <bitOffset>0</bitOffset>
              <bitWidth>8</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>DOR1</name>
          <displayName>DOR1</displayName>
          <description>channel1 data output register</description>
          <addressOffset>0x2C</addressOffset>
          <size>0x20</size>
          <access>read-only</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DACC1DOR</name>
              <description>DAC channel1 data output</description>
              <bitOffset>0</bitOffset>
              <bitWidth>12</bitWidth>
            </field>
          </fields>
        </register>
        <register>
          <name>SR</name>
          <displayName>SR</displayName>
          <description>status register</description>
          <addressOffset>0x34</addressOffset>
          <size>0x20</size>
          <access>read-write</access>
          <resetValue>0x00000000</resetValue>
          <fields>
            <field>
              <name>DMAUDR2</name>
              <description>DAC channel2 DMA underrun
              flag</description>
              <bitOffset>29</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
            <field>
              <name>DMAUDR1</name>
              <description>DAC channel1 DMA underrun
              flag</description>
              <bitOffset>13</bitOffset>
              <bitWidth>1</bitWidth>
            </field>
          </fields>
        </register>
      </registers>
    </peripheral>

上述中间段落为增加的代码，支持中文；
文中仅增加了dac2的cr寄存器的说明，相信细心的小伙伴就可以自己按照格式添加了。