What is Clock Gating?
• Register banks disabled during some clock cycles
– Typical implementation uses multiplexers
– Clock gating cell replaces multiplexers
典型RTL设计:
RTL:
时序图:
What is Clock Gating?
• Register banks disabled during some clock cycles
– Typical implementation uses multiplexers
– Clock gating cell replaces multiplexers
典型RTL设计:
RTL:
时序图:
转载于:https://www.cnblogs.com/zxmind/p/8706497.html