zynq_devicetree

device tree最开始的是skeleton.dtsi

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  1.  http://blog.csdn.net/shichaog/article/details/51249106
  2. /*
  3.  * Skeleton device tree; the bare minimum needed to boot; just include and  
  4.  * add a compatible value.  The bootloader will typically populate the memory  
  5.  * node.  
  6.  */  
  7.   
  8. / {  
  9.     #address-cells = <1>;  
  10.     #size-cells = <1>;  
  11.     chosen { };  
  12.     aliases { };  
  13.     memory { device_type = "memory"; reg = <0 0>; };  
  14. };  

这是32位体系架构的设备树的skeleton,address-cells那行表示的是用32bit表示地址,寄存器也是用32bit来表示。接下来设备树里的东西是和zynq-7000这款芯片cpu息息相关的定义。将cpu以及外设都定义在此处。

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  1. 《zynq-7000.dtsi》  
  2.   1 /*  
  3.   2  *  Copyright (C) 2011 - 2014 Xilinx  
  4.   3  *  
  5.   4  * This software is licensed under the terms of the GNU General Public  
  6.   5  * License version 2, as published by the Free Software Foundation, and  
  7.   6  * may be copied, distributed, and modified under those terms.  
  8.   7  *  
  9.   8  * This program is distributed in the hope that it will be useful,  
  10.   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of  
  11.  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
  12.  11  * GNU General Public License for more details.  
  13.  12  */  
  14.  13 /include/ "skeleton.dtsi"  
  15.  14   
  16.  15 / {  
  17.  16     compatible = "xlnx,zynq-7000";  
  18.  17   
  19.  18     cpus {  
  20.  19         #address-cells = <1>;  
  21.  20         #size-cells = <0>;  
  22.  21   
  23.  22         cpu@0 {  
  24.  23             compatible = "arm,cortex-a9";  
  25.  24             device_type = "cpu";  
  26.  25             reg = <0>;  
  27.  26             clocks = <&clkc 3>;  
  28.  27             clock-latency = <1000>;  
  29.  28             cpu0-supply = <&regulator_vccpint>;  
  30.  29             operating-points = <  
  31.  30                 /* kHz    uV */  
  32.  31                 666667  1000000  
  33.  32                 333334  1000000  
  34.  33             >;  
  35.  34         };  
  36.  35   
  37.  36         cpu@1 {  
  38.  37             compatible = "arm,cortex-a9";  
  39.  38             device_type = "cpu";  
  40.  39             reg = <1>;  
  41.  40             clocks = <&clkc 3>;  
  42.  41         };  
  43.  42     };  
  44.  43   
  45.  44     pmu {  
  46.  45         compatible = "arm,cortex-a9-pmu";  
  47.  46         interrupts = <0 5 4>, <0 6 4>;  
  48.  47         interrupt-parent = <&intc>;  
  49.  48         reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;  
  50.  49     };  
  51.  50   
  52.  51     regulator_vccpint: fixedregulator@0 {  
  53.  52         compatible = "regulator-fixed";  
  54.  53         regulator-name = "VCCPINT";  
  55.  54         regulator-min-microvolt = <1000000>;  
  56.  55         regulator-max-microvolt = <1000000>;  
  57.  56         regulator-boot-on;  
  58.  57         regulator-always-on;  
  59.  58     };  
  60.  59   
  61.  60     amba: amba {  
  62.  61         compatible = "simple-bus";  
  63.  62         #address-cells = <1>;  
  64.  63         #size-cells = <1>;  
  65.  64         interrupt-parent = <&intc>;  
  66.  65         ranges;  
  67.  66   
  68.  67         adc: adc@f8007100 {  
  69.  68             compatible = "xlnx,zynq-xadc-1.00.a";  
  70.  69             reg = <0xf8007100 0x20>;  
  71.  70             interrupts = <0 7 4>;  
  72.  71             interrupt-parent = <&intc>;  
  73.  72             clocks = <&clkc 12>;  
  74.  73         };  
  75.  74   
  76.  75         can0: can@e0008000 {  
  77.  76             compatible = "xlnx,zynq-can-1.0";  
  78.  77             status = "disabled";  
  79.  78             clocks = <&clkc 19>, <&clkc 36>;  
  80.  79             clock-names = "can_clk", "pclk";  
  81.  80             reg = <0xe0008000 0x1000>;  
  82.  81             interrupts = <0 28 4>;  
  83.  82             interrupt-parent = <&intc>;  
  84.  83             tx-fifo-depth = <0x40>;  
  85.  84             rx-fifo-depth = <0x40>;  
  86.  85         };  
  87.  86   
  88.  87         can1: can@e0009000 {  
  89.  88             compatible = "xlnx,zynq-can-1.0";  
  90.  89             status = "disabled";  
  91.  90             clocks = <&clkc 20>, <&clkc 37>;  
  92.  91             clock-names = "can_clk", "pclk";  
  93.  92             reg = <0xe0009000 0x1000>;  
  94.  93             interrupts = <0 51 4>;  
  95.  94             interrupt-parent = <&intc>;  
  96.  95             tx-fifo-depth = <0x40>;  
  97.  96             rx-fifo-depth = <0x40>;  
  98.  97         };  
  99.  98   
  100.  99         gpio0: gpio@e000a000 {  
  101. 100             compatible = "xlnx,zynq-gpio-1.0";  
  102. 101             #gpio-cells = <2>;  
  103. 102             #interrupt-cells = <2>;  
  104. 103             clocks = <&clkc 42>;  
  105. 104             gpio-controller;  
  106. 105             interrupt-controller;  
  107. 106             interrupt-parent = <&intc>;  
  108. 107             interrupts = <0 20 4>;  
  109. 108             reg = <0xe000a000 0x1000>;  
  110. 109         };  
  111. 110   
  112. 111         i2c0: i2c@e0004000 {  
  113. 112             compatible = "cdns,i2c-r1p10";  
  114. 113             status = "disabled";  
  115. 114             clocks = <&clkc 38>;  
  116. 115             interrupt-parent = <&intc>;  
  117. 116             interrupts = <0 25 4>;  
  118. 117             reg = <0xe0004000 0x1000>;  
  119. 118             #address-cells = <1>;  
  120. 119             #size-cells = <0>;  
  121. 120         };  
  122. 121   
  123. 122         i2c1: i2c@e0005000 {  
  124. 123             compatible = "cdns,i2c-r1p10";  
  125. 124             status = "disabled";  
  126. 125             clocks = <&clkc 39>;  
  127. 126             interrupt-parent = <&intc>;  
  128. 127             interrupts = <0 48 4>;  
  129. 128             reg = <0xe0005000 0x1000>;  
  130. 129             #address-cells = <1>;  
  131. 130             #size-cells = <0>;  
  132. 131         };  
  133. 132   
  134. 133         intc: interrupt-controller@f8f01000 {  
  135. 134             compatible = "arm,cortex-a9-gic";  
  136. 135             #interrupt-cells = <3>;  
  137. 136             interrupt-controller;  
  138. 137             reg = <0xF8F01000 0x1000>,  
  139. 138                   <0xF8F00100 0x100>;  
  140. 139         };  
  141. 140   
  142. 141         L2: cache-controller@f8f02000 {  
  143. 142             compatible = "arm,pl310-cache";  
  144. 143             reg = <0xF8F02000 0x1000>;  
  145. 144             interrupts = <0 2 4>;  
  146. 145             arm,data-latency = <3 2 2>;  
  147. 146             arm,tag-latency = <2 2 2>;  
  148. 147             cache-unified;  
  149. 148             cache-level = <2>;  
  150. 149         };  
  151. 150   
  152. 151         mc: memory-controller@f8006000 {  
  153. 152             compatible = "xlnx,zynq-ddrc-a05";  
  154. 153             reg = <0xf8006000 0x1000>;  
  155. 154         };  
  156. 155   
  157. 156         ocmc: ocmc@f800c000 {  
  158. 157             compatible = "xlnx,zynq-ocmc-1.0";  
  159. 158             interrupt-parent = <&intc>;  
  160. 159             interrupts = <0 3 4>;  
  161. 160             reg = <0xf800c000 0x1000>;  
  162. 161         };  
  163. 162   
  164. 163         uart0: serial@e0000000 {  
  165. 164             compatible = "xlnx,xuartps", "cdns,uart-r1p8";  
  166. 165             status = "disabled";  
  167. 166             clocks = <&clkc 23>, <&clkc 40>;  
  168. 167             clock-names = "uart_clk", "pclk";  
  169. 168             reg = <0xE0000000 0x1000>;  
  170. 169             interrupts = <0 27 4>;  
  171. 170         };  
  172. 171   
  173. 172         uart1: serial@e0001000 {  
  174. 173             compatible = "xlnx,xuartps", "cdns,uart-r1p8";  
  175. 174             status = "disabled";  
  176. 175             clocks = <&clkc 24>, <&clkc 41>;  
  177. 176             clock-names = "uart_clk", "pclk";  
  178. 177             reg = <0xE0001000 0x1000>;  
  179. 178             interrupts = <0 50 4>;  
  180. 179         };  
  181. 180   
  182. 181         spi0: spi@e0006000 {  
  183. 182             compatible = "xlnx,zynq-spi-r1p6";  
  184. 183             reg = <0xe0006000 0x1000>;  
  185. 184             status = "disabled";  
  186. 185             interrupt-parent = <&intc>;  
  187. 186             interrupts = <0 26 4>;  
  188. 187             clocks = <&clkc 25>, <&clkc 34>;  
  189. 188             clock-names = "ref_clk", "pclk";  
  190. 189             #address-cells = <1>;  
  191. 190             #size-cells = <0>;  
  192. 191         };  
  193. 192   
  194. 193         spi1: spi@e0007000 {  
  195. 194             compatible = "xlnx,zynq-spi-r1p6";  
  196. 195             reg = <0xe0007000 0x1000>;  
  197. 196             status = "disabled";  
  198. 197             interrupt-parent = <&intc>;  
  199. 198             interrupts = <0 49 4>;  
  200. 199             clocks = <&clkc 26>, <&clkc 35>;  
  201. 200             clock-names = "ref_clk", "pclk";  
  202. 201             #address-cells = <1>;  
  203. 202             #size-cells = <0>;  
  204. 203         };  
  205. 204   
  206. 205         qspi: spi@e000d000 {  
  207. 206             clock-names = "ref_clk", "pclk";  
  208. 207             clocks = <&clkc 10>, <&clkc 43>;  
  209. 208             compatible = "xlnx,zynq-qspi-1.0";  
  210. 209             status = "disabled";  
  211. 210             interrupt-parent = <&intc>;  
  212. 211             interrupts = <0 19 4>;  
  213. 212             reg = <0xe000d000 0x1000>;  
  214. 213             #address-cells = <1>;  
  215. 214             #size-cells = <0>;  
  216. 215         };  
  217. 216   
  218. 217         smcc: memory-controller@e000e000 {  
  219. 218             #address-cells = <1>;  
  220. 219             #size-cells = <1>;  
  221. 220             status = "disabled";  
  222. 221             clock-names = "memclk", "aclk";  
  223. 222             clocks = <&clkc 11>, <&clkc 44>;  
  224. 223             compatible = "arm,pl353-smc-r2p1";  
  225. 224             interrupt-parent = <&intc>;  
  226. 225             interrupts = <0 18 4>;  
  227. 226             ranges ;  
  228. 227             reg = <0xe000e000 0x1000>;  
  229. 228             nand0: flash@e1000000 {  
  230. 229                 status = "disabled";  
  231. 230                 compatible = "arm,pl353-nand-r2p1";  
  232. 231                 reg = <0xe1000000 0x1000000>;  
  233. 232                 #address-cells = <0x1>;  
  234. 233                 #size-cells = <0x1>;  
  235. 234             };  
  236. 235             nor0: flash@e2000000 {  
  237. 236                 status = "disabled";  
  238. 237                 compatible = "cfi-flash";  
  239. 238                 reg = <0xe2000000 0x2000000>;  
  240. 239                 #address-cells = <1>;  
  241. 240                 #size-cells = <1>;  
  242. 241             };  
  243. 242         };  
  244. 243   
  245. 244         gem0: ethernet@e000b000 {  
  246. 245             compatible = "cdns,zynq-gem", "cdns,gem";  
  247. 246             reg = <0xe000b000 0x1000>;  
  248. 247             status = "disabled";  
  249. 248             interrupts = <0 22 4>;  
  250. 249             clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;  
  251. 250             clock-names = "pclk", "hclk", "tx_clk";  
  252. 251             #address-cells = <1>;  
  253. 252             #size-cells = <0>;  
  254. 253         };  
  255. 254   
  256. 255         gem1: ethernet@e000c000 {  
  257. 256             compatible = "cdns,zynq-gem", "cdns,gem";  
  258. 257             reg = <0xe000c000 0x1000>;  
  259. 258             status = "disabled";  
  260. 259             interrupts = <0 45 4>;  
  261. 260             clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;  
  262. 261             clock-names = "pclk", "hclk", "tx_clk";  
  263. 262             #address-cells = <1>;  
  264. 263             #size-cells = <0>;  
  265. 264         };  
  266. 265   
  267. 266         sdhci0: sdhci@e0100000 {  
  268. 267             compatible = "arasan,sdhci-8.9a";  
  269. 268             status = "disabled";  
  270. 269             clock-names = "clk_xin", "clk_ahb";  
  271. 270             clocks = <&clkc 21>, <&clkc 32>;  
  272. 271             interrupt-parent = <&intc>;  
  273. 272             interrupts = <0 24 4>;  
  274. 273             reg = <0xe0100000 0x1000>;  
  275. 274         };  
  276. 275   
  277. 276         sdhci1: sdhci@e0101000 {  
  278. 277             compatible = "arasan,sdhci-8.9a";  
  279. 278             status = "disabled";  
  280. 279             clock-names = "clk_xin", "clk_ahb";  
  281. 280             clocks = <&clkc 22>, <&clkc 33>;  
  282. 281             interrupt-parent = <&intc>;  
  283. 282             interrupts = <0 47 4>;  
  284. 283             reg = <0xe0101000 0x1000>;  
  285. 284         };  
  286. 285   
  287. 286         slcr: slcr@f8000000 {  
  288. 287             #address-cells = <1>;  
  289. 288             #size-cells = <1>;  
  290. 289             compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";  
  291. 290             reg = <0xF8000000 0x1000>;  
  292. 291             ranges;  
  293. 292             clkc: clkc@100 {  
  294. 293                 #clock-cells = <1>;  
  295. 294                 compatible = "xlnx,ps7-clkc";  
  296. 295                 fclk-enable = <0xf>;  
  297. 296                 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",  
  298. 297                         "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",  
  299. 298                         "dci", "lqspi", "smc", "pcap", "gem0", "gem1",  
  300. 299                         "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",  
  301. 300                         "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",  
  302. 301                         "dma", "usb0_aper", "usb1_aper", "gem0_aper",  
  303. 302                         "gem1_aper", "sdio0_aper", "sdio1_aper",  
  304. 303                         "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",  
  305. 304                         "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",  
  306. 305                         "gpio_aper", "lqspi_aper", "smc_aper", "swdt",  
  307. 306                         "dbg_trc", "dbg_apb";  
  308. 307                 reg = <0x100 0x100>;  
  309. 308             };  
  310. 309   
  311. 310             rstc: rstc@200 {  
  312. 311                 compatible = "xlnx,zynq-reset";  
  313. 312                 reg = <0x200 0x48>;  
  314. 313                 #reset-cells = <1>;  
  315. 314                 syscon = <&slcr>;  
  316. 315             };  
  317. 316   
  318. 317             pinctrl0: pinctrl@700 {  
  319. 318                 compatible = "xlnx,pinctrl-zynq";  
  320. 319                 reg = <0x700 0x200>;  
  321. 320                 syscon = <&slcr>;  
  322. 321             };  
  323. 322         };  
  324. 323   
  325. 324         dmac_s: dmac@f8003000 {  
  326. 325             compatible = "arm,pl330", "arm,primecell";  
  327. 326             reg = <0xf8003000 0x1000>;  
  328. 327             interrupt-parent = <&intc>;  
  329. 328             interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",  
  330. 329                 "dma4", "dma5", "dma6", "dma7";  
  331. 330             interrupts = <0 13 4>,  
  332. 331                          <0 14 4>, <0 15 4>,  
  333. 332                          <0 16 4>, <0 17 4>,  
  334. 333                          <0 40 4>, <0 41 4>,  
  335. 334                          <0 42 4>, <0 43 4>;  
  336. 335             #dma-cells = <1>;  
  337. 336             #dma-channels = <8>;  
  338. 337             #dma-requests = <4>;  
  339. 338             clocks = <&clkc 27>;  
  340. 339             clock-names = "apb_pclk";  
  341. 340         };  
  342. 341   
  343. 342         devcfg: devcfg@f8007000 {  
  344. 343             compatible = "xlnx,zynq-devcfg-1.0";  
  345. 344             interrupt-parent = <&intc>;  
  346. 345             interrupts = <0 8 4>;  
  347. 346             reg = <0xf8007000 0x100>;  
  348. 347             clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;  
  349. 348             clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";  
  350. 349             syscon = <&slcr>;  
  351. 350         };  
  352. 351   
  353. 352         global_timer: timer@f8f00200 {  
  354. 353             compatible = "arm,cortex-a9-global-timer";  
  355. 354             reg = <0xf8f00200 0x20>;  
  356. 355             interrupts = <1 11 0x301>;  
  357. 356             interrupt-parent = <&intc>;  
  358. 357             clocks = <&clkc 4>;  
  359. 358         };  
  360. 359   
  361. 360         ttc0: timer@f8001000 {  
  362. 361             interrupt-parent = <&intc>;  
  363. 362             interrupts = <0 10 4>, <0 11 4>, <0 12 4>;  
  364. 363             compatible = "cdns,ttc";  
  365. 364             clocks = <&clkc 6>;  
  366. 365             reg = <0xF8001000 0x1000>;  
  367. 366         };  
  368. 367   
  369. 368         ttc1: timer@f8002000 {  
  370. 369             interrupt-parent = <&intc>;  
  371. 370             interrupts = <0 37 4>, <0 38 4>, <0 39 4>;  
  372. 371             compatible = "cdns,ttc";  
  373. 372             clocks = <&clkc 6>;  
  374. 373             reg = <0xF8002000 0x1000>;  
  375. 374         };  
  376. 375   
  377. 376         scutimer: timer@f8f00600 {  
  378. 377             interrupt-parent = <&intc>;  
  379. 378             interrupts = <1 13 0x301>;  
  380. 379             compatible = "arm,cortex-a9-twd-timer";  
  381. 380             reg = <0xf8f00600 0x20>;  
  382. 381             clocks = <&clkc 4>;  
  383. 382         };  
  384. 383   
  385. 384         usb0: usb@e0002000 {  
  386. 385             compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";  
  387. 386             status = "disabled";  
  388. 387             clocks = <&clkc 28>;  
  389. 388             interrupt-parent = <&intc>;  
  390. 389             interrupts = <0 21 4>;  
  391. 390             reg = <0xe0002000 0x1000>;  
  392. 391             phy_type = "ulpi";  
  393. 392         };  
  394. 393   
  395. 394         usb1: usb@e0003000 {  
  396. 395             compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";  
  397. 396             status = "disabled";  
  398. 397             clocks = <&clkc 29>;  
  399. 398             interrupt-parent = <&intc>;  
  400. 399             interrupts = <0 44 4>;  
  401. 400             reg = <0xe0003000 0x1000>;  
  402. 401             phy_type = "ulpi";  
  403. 402         };  
  404. 403   
  405. 404         watchdog0: watchdog@f8005000 {  
  406. 405             clocks = <&clkc 45>;  
  407. 406             compatible = "cdns,wdt-r1p2";  
  408. 407             interrupt-parent = <&intc>;  
  409. 408             interrupts = <0 9 1>;  
  410. 409             reg = <0xf8005000 0x1000>;  
  411. 410             timeout-sec = <10>;  
  412. 411         };  
  413. 412     };  
  414. 413 };  
接下来是对上面定义的节点一些属性的补充。

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  1. 《zynq.dtsi》  
  2.  1   
  3.   2 /include/ "zynq-7000.dtsi"  
  4.   3   
  5.   4 /*  
  6.   5  * The Xilinx EMACPS and the Cadance GEM drivers are for the same IP core, but  
  7.   6  * the drivers are not fully feature compatible. We stay with the Xilinx driver  
  8.   7  * for now. The main issue is the lack of support for gmii2rgmii when using the  
  9.   8  * Cadance driver.  
  10.   9  */  
  11.  10 &amba {  
  12.  11     eth: eth@e000b000 {  
  13.  12         compatible = "xlnx,ps7-ethernet-1.00.a";  
  14.  13         reg = <0xe000b000 0x1000>;  
  15.  14         interrupts = <0 22 4>;  
  16.  15         interrupt-parent = <&intc>;  
  17.  16         #address-cells = <0x1>;  
  18.  17         #size-cells = <0x0>;  
  19.  18   
  20.  19         clock-names = "ref_clk", "aper_clk";  
  21.  20         clocks = <&clkc 13>, <&clkc 30>;  
  22.  21   
  23.  22         xlnx,enet-clk-freq-hz = <0x17d7840>;  
  24.  23         xlnx,enet-reset = "MIO 11";  
  25.  24         xlnx,enet-slcr-1000mbps-div0 = <0x8>;  
  26.  25         xlnx,enet-slcr-1000mbps-div1 = <0x1>;  
  27.  26         xlnx,enet-slcr-100mbps-div0 = <0x8>;  
  28.  27         xlnx,enet-slcr-100mbps-div1 = <0x5>;  
  29.  28         xlnx,enet-slcr-10mbps-div0 = <0x8>;  
  30.  29         xlnx,enet-slcr-10mbps-div1 = <0x32>;  
  31.  30         xlnx,eth-mode = <0x1>;  
  32.  31         xlnx,has-mdio = <0x1>;  
  33.  32         xlnx,ptp-enet-clock = <111111115>;  
  34.  33     };  
  35.  34   
  36.  35 };  
  37.  36   
  38.  37 /delete-node/ &gem0;  
  39.  38 /delete-node/ &gem1;  
  40.  39   
  41.  40 / {  
  42.  41     interrupt-parent = <&intc>;  
  43.  42   
  44.  43     aliases: aliases {  
  45.  44         ethernet0 = ð  
  46.  45         serial0 = &uart1;  
  47.  46     };  
  48.  47 };  
  49.  48   
  50.  49 &usb0 {  
  51.  50     status = "okay";  
  52.  51     dr_mode = "host"; /* This breaks OTG mode */  
  53.  52 };  
  54.  53   
  55.  54 &uart1 {  
  56.  55     status = "okay";  
  57.  56 };  
  58.  57   
  59.  58 &sdhci0 {  
  60.  59     status = "okay";  
  61.  60 };  
接下来是板级节点属性的定义, memory的reg属性表示内存的起始地址是0,大小是0x2000_0000(512M),这正是板子内存大小。

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  1. 《zynq-zed.dtsi》  
  2.  1 /include/ "zynq.dtsi"  
  3.   2   
  4.   3 / {  
  5.   4     model = "Xilinx Zynq ZED";  
  6.   5     memory {  
  7.   6         device_type = "memory";  
  8.   7         reg = <0x000000000 0x20000000>;  
  9.   8     };  
  10.   9   
  11.  10     chosen {  
  12.  11 //      bootargs = "console=ttyPS0,115200 root=/dev/ram rw initrd=0x1100000,33M ip=:::::eth0:dhcp earlyprintk";  
  13.  12         bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait";  
  14.  13         linux,stdout-path = "/amba@0/uart@E0001000";  
  15.  14     };  
  16.  15 };  
  17.  16   
  18.  17 &eth {  
  19.  18     phy-handle = <&phy0>;  
  20.  19     phy-mode = "rgmii-id";  
  21.  20   
  22.  21     phy0: phy@0 {  
  23.  22         compatible = "marvell,88e1510";  
  24.  23         device_type = "ethernet-phy";  
  25.  24         reg = <0x0>;  
  26.  25         marvell,reg-init=<3 16 0xff00 0x1e 3 17 0xfff0 0x0a>;  
  27.  26     };  
  28.  27 };  
  29.  28   
  30.  29 &usb0 {  
  31.  30     xlnx,phy-reset-gpio = <&gpio0 85 0>;  
  32.  31 };  
  33.  32   
  34.  33 &qspi {  
  35.  34     status = "okay";  
  36.  35     is-dual = <0>;  
  37.  36     num-cs = <1>;  
  38.  37     primary_flash: ps7-qspi@0 {  
  39.  38         #address-cells = <1>;  
  40.  39         #size-cells = <1>;  
  41.  40         compatible = "n25q128a11";  
  42.  41         reg = <0x0>;  
  43.  42         spi-max-frequency = <50000000>;  
  44.  43         partition@0x00000000 {  
  45.  44             label = "boot";  
  46.  45             reg = <0x00000000 0x00500000>;  
  47.  46         };  
  48.  47         partition@0x00500000 {  
  49.  48             label = "bootenv";  
  50.  49             reg = <0x00500000 0x00020000>;  
  51.  50         };  
  52.  51         partition@0x00520000 {  
  53.  52             label = "config";  
  54.  53             reg = <0x00520000 0x00020000>;  
  55.  54         };  
  56.  55         partition@0x00540000 {  
  57.  56             label = "image";  
  58.  57             reg = <0x00540000 0x00a80000>;  
  59.  58         };  
  60.  59         partition@0x00fc0000 {  
  61.  60             label = "spare";  
  62.  61             reg = <0x00fc0000 0x00000000>;  
  63.  62         };  
  64.  63     };  
  65.  64 };  
在下来,就是这里使用了hdmi视频和zed board上的音频以及其它外设资源定义了,这些外设使用了PL(program logic资源,即FPGA资源)。

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  1. 《zynq-zed-adv7511.dtsi》  
  2.  1 / {  
  3.   2     fpga_axi: fpga-axi@0 {  
  4.   3         compatible = "simple-bus";  
  5.   4         #address-cells = <0x1>;  
  6.   5         #size-cells = <0x1>;  
  7.   6         ranges;  
  8.   7   
  9.   8         i2c@41600000 {  
  10.   9             compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a";  
  11.  10             interrupt-parent = <&intc>;  
  12.  11             interrupts = <0 58 0x4>;  
  13.  12             reg = <0x41600000 0x10000>;  
  14.  13   
  15.  14             #size-cells = <0>;  
  16.  15             #address-cells = <1>;  
  17.  16   
  18.  17             adv7511: adv7511@39 {  
  19.  18                 compatible = "adi,adv7511";  
  20.  19                 reg = <0x39>;  
  21.  20   
  22.  21                 adi,input-style = <0x02>;  
  23.  22                 adi,input-id = <0x01>;  
  24.  23                 adi,input-color-depth = <0x3>;  
  25.  24                 adi,sync-pulse = <0x03>;  
  26.  25                 adi,bit-justification = <0x01>;  
  27.  26                 adi,up-conversion = <0x00>;  
  28.  27                 adi,timing-generation-sequence = <0x00>;  
  29.  28                 adi,vsync-polarity = <0x02>;  
  30.  29                 adi,hsync-polarity = <0x02>;  
  31.  30                 adi,tdms-clock-inversion;  
  32.  31                 adi,clock-delay = <0x03>;  
  33.  32   
  34.  33                 ports {  
  35.  34                     #address-cells = <1>;  
  36.  35                     #size-cells = <0>;  
  37.  36   
  38.  37                     port@0 {  
  39.  38                         reg = <0>;  
  40.  39                         adv7511_in: endpoint {  
  41.  40                             remote-endpoint = <&axi_hdmi_out>;  
  42.  41                         };  
  43.  42                     };  
  44.  43   
  45.  44                     port@1 {  
  46.  45                         reg = <1>;  
  47.  46                     };  
  48.  47                 };  
  49.  48             };  
  50.  49   
  51.  50             adau1761: adau1761@3b {  
  52.  51                 compatible = "adi,adau1761";  
  53.  52                 reg = <0x3b>;  
  54.  53             };  
  55.  54         };  
  56.  55   
  57.  56         axi_vdma_0: axivdma@43000000 {  
  58.  57             compatible = "xlnx,axi-vdma-1.00.a";  
  59.  58             #address-cells = <1>;  
  60.  59             #size-cells = <1>;  
  61.  60             #dma-cells = <1>;  
  62.  61             #dma-channels = <1>;  
  63.  62             reg = <0x43000000 0x1000>;  
  64.  63             xlnx,num-fstores = <0x3>;  
  65.  64             dma-channel@43000000 {  
  66.  65                 compatible = "xlnx,axi-vdma-mm2s-channel";  
  67.  66                 interrupts = <0 59 0x4>;  
  68.  67                 xlnx,datawidth = <0x40>;  
  69.  68                 xlnx,genlock-mode = <0x0>;  
  70.  69                 xlnx,include-dre = <0x0>;  
  71.  70             };  
  72.  71         };  
  73.  72   
  74.  73         hdmi_clock: axi-clkgen@79000000 {  
  75.  74             compatible = "adi,axi-clkgen-2.00.a";  
  76.  75             reg = <0x79000000 0x10000>;  
  77.  76             #clock-cells = <0>;  
  78.  77             clocks = <&clkc 16>;  
  79.  78         };  
  80.  79   
  81.  80         axi_hdmi@70e00000 {  
  82.  81             compatible = "adi,axi-hdmi-tx-1.00.a";  
  83.  82             reg = <0x70e00000 0x10000>;  
  84.  83             dmas = <&axi_vdma_0 0>;  
  85.  84             dma-names = "video";  
  86.  85             clocks = <&hdmi_clock>;  
  87.  86   
  88.  87             port {  
  89.  88                 axi_hdmi_out: endpoint {  
  90.  89                     remote-endpoint = <&adv7511_in>;  
  91.  90                 };  
  92.  91             };  
  93.  92         };  
  94.  93   
  95.  94         audio_clock: audio_clock {  
  96.  95             compatible = "fixed-clock";  
  97.  96             #clock-cells = <0>;  
  98.  97             clock-frequency = <12288000>;  
  99.  98         };  
  100.  99   
  101. 100         axi_spdif_tx_0: axi-spdif-tx@0x75c00000 {  
  102. 101             compatible = "adi,axi-spdif-tx-1.00.a";  
  103. 102             reg = <0x75c00000 0x1000>;  
  104. 103             dmas = <&dmac_s 0>;  
  105. 104             dma-names = "tx";  
  106. 105             clocks = <&clkc 15>, <&audio_clock>;  
  107. 106             clock-names = "axi", "ref";  
  108. 107         };  
  109. 108   
  110. 109         adv7511_hdmi_snd: adv7511_hdmi_snd {  
  111. 110             compatible = "adv7511-hdmi-snd";  
  112. 111             audio-codec = <&adv7511>;  
  113. 112             cpu-dai = <&axi_spdif_tx_0>;  
  114. 113         };  
  115. 114   
  116. 115         axi_i2s_0: axi-i2s@0x77600000 {  
  117. 116             compatible = "adi,axi-i2s-1.00.a";  
  118. 117             reg = <0x77600000 0x1000>;  
  119. 118             dmas = <&dmac_s 1 &dmac_s 2>;  
  120. 119             dma-names = "tx", "rx";  
  121. 120             clocks = <&clkc 15>, <&audio_clock>;  
  122. 121             clock-names = "axi", "ref";  
  123. 122         };  
  124. /* 第116行的字段和<sound/soc/adi/axi-i2s.c>的260行相互匹配,reg这个字段在vivado的block design中Address Editor可以看出0x77600000是i2s是基地址,  
  125. 0x1000是寄存器段的大小,dmas是dma字段,使用了PS端的dmac 1和dmac 2,dmac 0在vivado的设计中并没有设备,所以spdif的驱动并没有注册,这两个dma分别用于发送和  
  126. 接收,clocks字段第一个是axi接口的时钟,第二个是iis的master时钟,这里就是12.288MHz。 这个IIS 控制器dai,实际上在PL里,但是相对adau1761这些外置dai而言,它们是cpu dai*/  
  127. 123   
  128. 124         zed_sound: zed_sound {  
  129. 125             compatible = "digilent,zed-sound";  
  130. 126             audio-codec = <&adau1761>;  
  131. 127             cpu-dai = <&axi_i2s_0>;  
  132. 128         };  
  133. /*这个字段的125行是和<sound/soc/adi/zed_adau1761.c> 的144相呼应的,设备树表示,adau1761将和axi_i2s_0进行音频数据交互,该文件描述了codec侧的dai*/  
  134.   
  135.   
  136.  129     };  
  137. 130   
  138. 131     leds {  
  139. 132         compatible = "gpio-leds";  
  140. 133         ld0 {  
  141. 134             label = "ld0:red";  
  142. 135             gpios = <&gpio0 73 0>;  
  143. 136         };  
  144. 137   
  145. 138         ld1 {  
  146. 139             label = "ld1:red";  
  147. 140             gpios = <&gpio0 74 0>;  
  148. 141         };  
  149. 142   
  150. 143         ld2 {  
  151. 144             label = "ld2:red";  
  152. 145             gpios = <&gpio0 75 0>;  
  153. 146         };  
  154. 147   
  155. 148         ld3 {  
  156. 149             label = "ld3:red";  
  157. 150             gpios = <&gpio0 76 0>;  
  158. 151         };  
  159. 152   
  160. 153         ld4 {  
  161. 154             label = "ld4:red";  
  162. 155             gpios = <&gpio0 77 0>;  
  163. 156         };  
  164. 157   
  165. 158         ld5 {  
  166. 159             label = "ld5:red";  
  167. 160             gpios = <&gpio0 78 0>;  
  168. 161         };  
  169. 162   
  170. 163         ld6 {  
  171. 164             label = "ld6:red";  
  172. 165             gpios = <&gpio0 79 0>;  
  173. 166         };  
  174. 167   
  175. 168         ld7 {  
  176. 169             label = "ld7:red";  
  177. 170             gpios = <&gpio0 80 0>;  
  178. 171         };  
  179. 172     };  
  180. 173 };  


interrupt节点:
interrupt-parent = <&intc1>;"interrupts" property, an "interrupts-extended" property, or both. If both are
present, the latter should take precedence; 
 //可继承
  interrupt-cells = <2>;//中断方式 
    - bits[3:0] trigger type and level flags
        1 = low-to-high edge triggered
        2 = high-to-low edge triggered
        4 = active high level-sensitive
        8 = active low level-sensitive

interrupts = <0 30 4>;
      The interrupt is chained to hardware interrupt 61 (29 + 32) of the GIC
      for Zynq.
  中断号:30+32
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