ISSI（芯成）—IS25WP512M-JLLA3 FLASH芯片详解-CSDN博客

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写在前面

本系列文章主要讲解ISSI（芯成）—IS25WP512M-JLLA3 FLASH芯片的相关知识，希望能帮助更多的同学认识和了解ISSI（芯成）—IS25WP512M-JLLA3 FLASH芯片。

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此次架构中IS25WP512M-JLLA3作为FLASH芯片使用，下面将详细介绍此芯片。

1. 描述

The IS25WP512M Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is for systems that require limited space, a low pin count, and low power consumption. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O.

The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66.5Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation.

QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64K/256Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention.

2. 特性

IS25WP512M: 512Mbit/64Mbyte,3 or 4 Byte Addressing Mode
Supports Standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI
Software & Hardware Reset
Supports Serial Flash Discoverable Parameters (SFDP)
IS25WP: 1.70V to 1.95V,13 mA Active Read Current,21 µA Standby Current,1 µA Deep Power Down
50MHz Normal Read,Up to133Mhz Fast Read:133MHz (max) for 3.0V,112MHz (max) for 1.8V
Up to 66MHz DTR (Dual Transfer Rate),Equivalent Throughput of 532 Mb/s,Selectable Dummy Cycles
Configurable Drive Strength,Supports SPI Modes 0 and 3,More than 100,000 Erase/Program Cycles
Chip Erase with Uniform Sector/Block Erase (4/32/64KB or 4/32/256 KB),Program 1 to 256 or 512 Byte per Page,Program/Erase Suspend & Resume
Low Instruction Overhead Operations,Continuous Read 8/16/32/64 Byte Burst Wrap
Selectable Burst Length,QPI for Reduced Instruction Overhead,Data Learning Pattern for training in DTR operation
Software and Hardware Write Protection,Advanced Sector/Block Protection,Top/Bottom Block Protection
Power Supply Lock Protection,4x256 Byte Dedicated Security Area with OTP User-lockable Bits,128 bit Unique ID for Each Device

3. 框架图

4. 引脚定义

PIN	Symbol	Description
1	CE#	The Chip Enable (CE#) pin enables and disables the devices operation. When CE# is high, the device is deselected and output pins are in a high impedance state. When deselected the devices non-critical internal circuitry power down to allow minimal levels of power consumption while in a standby state.
2	SO (IO1)	This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI instructions use the unidirectional SI (Serial Input) pin to write instructions, addresses, or data to the device on the rising edge of the Serial Clock (SCK). Standard SPI also uses the unidirectional SO (Serial Output) to read data or status from the device on the falling edge of the serial clock (SCK).
3	WP# (IO2)	The WP# pin protects the Status Register from being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the Status Register is not write-protected regardless of WP# state.
4	GND	Connect to ground when referenced to Vcc
5	SI (IO0)	This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI instructions use the unidirectional SI (Serial Input) pin to write instructions, addresses, or data to the device on the rising edge of the Serial Clock (SCK). Standard SPI also uses the unidirectional SO (Serial Output) to read data or status from the device on the falling edge of the serial clock (SCK).
6	SCK	Synchronized Clock for input and output timing operations.
7	HOLD# (IO3)	When the QE bit of Status Register is set to “1”, HOLD# pin or RESET# is not available since it becomes IO3.
8	Vcc	Device Core Power Supply