SystemVerilog开源编译解析工具slang入门2：单步调试

I_belong_to_jesus

已于 2024-02-26 16:12:53 修改

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分类专栏： FPGA+EDA 文章标签：开源 c++

于 2022-10-25 00:50:30 首次发布

本文链接：https://blog.csdn.net/fangfanglovezhou/article/details/127505581

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上一节介绍了编译和安装，本节介绍下如何使用VisualStudio进行单步调试，在VisualStudio界面中的调试下面选择调试和启动driver设置配置单步调试的配置

配置的lauch.vs.json文件内容如下：

{
  "version": "0.2.1",
  "defaults": {},
  "configurations": [
    {
      "type": "default",
      "project": "CMakeLists.txt",
      "projectTarget": "slang.exe (bin\\slang.exe)",
      "name": "slang.exe (bin\\slang.exe)",
        "args": [
            "F:\\test\\multi_logic.v",
            "--ast-json",
            "F:\\ast.json"
        ]
    }
  ]
}

这里编译的muti_logic.v文件内容为：

module multi_logic (a,clk,ou);
	input a,clk;
	output ou;      
	reg a,clk,ou;           
	always @(posedge clk) begin
        ou <= a;
	end
endmodule

执行调试指令，执行完成后结果如下图：

对应位置会生成对应的语法树对应的.json文件ast.json，内容为：

{
  "name": "$root",
  "kind": "Root",
  "addr": 2161194855600,
  "members": [
    {
      "name": "",
      "kind": "CompilationUnit",
      "addr": 2161195038752
    },
    {
      "name": "multi_logic",
      "kind": "Instance",
      "addr": 2161195041392,
      "body": {
        "name": "multi_logic",
        "kind": "InstanceBody",
        "addr": 2161195039120,
        "members": [
          {
            "name": "a",
            "kind": "Port",
            "addr": 2161195041512,
            "type": "reg",
            "direction": "In",
            "internalSymbol": "2161195040736 a"
          },
          {
            "name": "clk",
            "kind": "Port",
            "addr": 2161195041688,
            "type": "reg",
            "direction": "In",
            "internalSymbol": "2161195040912 clk"
          },
          {
            "name": "ou",
            "kind": "Port",
            "addr": 2161195041864,
            "type": "reg",
            "direction": "Out",
            "internalSymbol": "2161195041088 ou"
          },
          {
            "name": "a",
            "kind": "Variable",
            "addr": 2161195040736,
            "type": "reg",
            "lifetime": "Static"
          },
          {
            "name": "clk",
            "kind": "Variable",
            "addr": 2161195040912,
            "type": "reg",
            "lifetime": "Static"
          },
          {
            "name": "ou",
            "kind": "Variable",
            "addr": 2161195041088,
            "type": "reg",
            "lifetime": "Static"
          },
          {
            "name": "",
            "kind": "ProceduralBlock",
            "addr": 2161195041264,
            "procedureKind": "Always",
            "body": {
              "kind": "Timed",
              "timing": {
                "kind": "SignalEvent",
                "expr": {
                  "kind": "NamedValue",
                  "type": "reg",
                  "symbol": "2161195040912 clk"
                },
                "edge": "PosEdge"
              },
              "stmt": {
                "kind": "Block",
                "blockKind": "Sequential",
                "body": {
                  "kind": "ExpressionStatement",
                  "expr": {
                    "kind": "Assignment",
                    "type": "reg",
                    "left": {
                      "kind": "NamedValue",
                      "type": "reg",
                      "symbol": "2161195041088 ou"
                    },
                    "right": {
                      "kind": "NamedValue",
                      "type": "reg",
                      "symbol": "2161195040736 a"
                    },
                    "isNonBlocking": true
                  }
                }
              }
            }
          }
        ],
        "definition": "multi_logic"
      },
      "connections": [
      ]
    }
  ]
}