ZedBoard Vivado 自定义IP流水灯
视频教程:http://t.elecfans.com/1428.html
讲师:刘俊飞 FPGA工程师
整理:s__w
步骤
新建工程
新建板图,文件格式 “.bd”
新建并封装IP
选择已经准备好的module_name.v文件,
flow_led.v
module flow_led(input clk, output [7:0] led);
reg [7:0] temp = 8'b0000_0001;//若直接用initial对led赋值,不可综合
reg [26:0] cnt;
always@(posedge clk)
begin
if(cnt == 10_000_000)
begin
temp[7:1]<=temp[6:0];
temp[0]<=temp[7];
cnt<=0;
end
else
cnt <= cnt + 1;
end
assign led = temp;
endmodule
package IP
(忽略黄色叹号)
在板图.bd文件中搜索并添加自定义的IP
添加管脚、定义管脚名称、方向、位宽
create port
鼠标箭头变成小铅笔,连接管脚
保存.bd
sources窗口,右键单击.bd文件,
create HDL wrapper 生成顶层.v文件
增加端口约束文件,文件格式.xdc
下载官方约束文件http://zedboard.org/support/documentation/1521
将约束文件中的 管脚约束 时钟:clock source 和 led灯:user led部分;以及电压约束 iostandard constraints 对应的部分复制到上一步新建的约束文件中。
根据板图,修改管脚名称,不要破坏原xdc文件格式
led_water_lights.xdc
# ----------------------------------------------------------------------------
# Clock Source - Bank 13
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN Y9 [get_ports {clk}]; # "GCLK"
# ----------------------------------------------------------------------------
# User LEDs - Bank 33
# ----------------------------------------------------------------------------
set_property PACKAGE_PIN T22 [get_ports {led[0]}]; # "LD0"
set_property PACKAGE_PIN T21 [get_ports {led[1]}]; # "LD1"
set_property PACKAGE_PIN U22 [get_ports {led[2]}]; # "LD2"
set_property PACKAGE_PIN U21 [get_ports {led[3]}]; # "LD3"
set_property PACKAGE_PIN V22 [get_ports {led[4]}]; # "LD4"
set_property PACKAGE_PIN W22 [get_ports {led[5]}]; # "LD5"
set_property PACKAGE_PIN U19 [get_ports {led[6]}]; # "LD6"
set_property PACKAGE_PIN U14 [get_ports {led[7]}]; # "LD7"
# ----------------------------------------------------------------------------
# IOSTANDARD Constraints
#
# Note that these IOSTANDARD constraints are applied to all IOs currently
# assigned within an I/O bank. If these IOSTANDARD constraints are
# evaluated prior to other PACKAGE_PIN constraints being applied, then
# the IOSTANDARD specified will likely not be applied properly to those
# pins. Therefore, bank wide IOSTANDARD constraints should be placed
# within the XDC file in a location that is evaluated AFTER all
# PACKAGE_PIN constraints within the target bank have been evaluated.
#
# Un-comment one or more of the following IOSTANDARD constraints according to
# the bank pin assignments that are required within a design.
# ----------------------------------------------------------------------------
# Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
# Set the bank voltage for IO Bank 34 to 1.8V by default.
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 34]];
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 34]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
# Set the bank voltage for IO Bank 35 to 1.8V by default.
# set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 35]];
# set_property IOSTANDARD LVCMOS25 [get_ports -of_objects [get_iobanks 35]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
# Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard.
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
生成比特文件,格式.bit
(弹出窗口:仿真、实现?Yes!)
(忽略如下 critical warning, 点击OK,不要close run)
打开硬件配置 Hardware manager
点击 自动连接 auto connect
右键FPGA(xc7z020)program device
选择比特文件(默认已经自动选择了上一步生成的.bit文件)
不用管debug,忽略如下warning
流水灯正常运行。(快门速度较慢)