【存储器】高速缓存器

计算机组织与结构

       In 【存储器】半导体存储器 we know that the SRAM is uesd for cache for its stable and high speed in writing and reading, and there is a memory hierarchy :

Why cache?

       Nowadays, the speed of CPU is faster than memory’s like this figure :

Basic Idea

1. Use a smaller, faster cache(SRAM) memory block together with a relatively large and slow main block(DRAM).
2. The cache contains a copy of portions of main memory.
3. Located between CPU and memory, and may be integrated inside CPU or as a module on motherboard.
   Like this :
   

How it works

1. Check : When the processor attempts to read a word of memory, a check is made to determine whether the word is in the cache.
2. Hit : If so, the word is delivered to the processor.
3. Miss : If not, a block of main memory, consisting of some fixed number of words, is read into the cache and then the word is delivered to the processor.
   Like this :
   

Questions

       We know how it works, but why we can solve the problem in this way, There are some questions and answers.

Q1 : How to determine hit and miss?

       Through the von Neumann machine, the contents of this memory are addressable by location, without regard to the type of data contained there. So cache includes tags to identify its content’s corresponding locations in main memory.

Q2 : Why not directly move the word from memory to CPU if miss?

       There is a phenomenon describing the same value, or related storage locations, being frequently accessed.
This three types :

• Temporal locality : the reuse of specific data, and/or resources, within a relatively small time duration.
• Spatial locality : the use of data elements within relatively close s