【原创】WIN10安装Modelsim10.4c及和谐

本文详述了在Windows 10系统上安装Modelsim10.4c的步骤,包括解决安装过程中遇到的问题,如运行patch_dll.bat时无法显示LICENSE.TXT。通过关闭杀毒软件、安装、复制patch_dll.bat和MentorKG.exe文件、修改文件属性、运行批处理脚本和配置环境变量等步骤,成功完成安装并能正常使用。
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【主题】:WIN10安装Modelsim10.4c及和谐

【作者】:LinCoding

【时间】:2017.05.19

       最近仿真一个SDRAM控制器,之前安装的Modelsim10.1c老是出现运行.do脚本后没反应的情况,所以就装了Modelsim10.4c,虽然按照网上的教程一步步来,但是在运行patch_dll.bat时候总是弹不出LICENSE.TXT,试了各种方法以后总算解决了。发出来大家共享下:

1、关闭杀毒软件

2、运行modelsim-win64-10.4-se.exe,选择默认的安装目录C:\modeltech64_10.4

3、安装过程始终点击yes,直到最后reboot,选择no

4、复制patch_dll.bat和MentorKG.exe到安装目录C:\modeltech64_10.4\win64</

Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
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