ddr3 仿真 &几个报错处理 - Warning - Carriage return (0x0D) is not followed by a newline (0x0A).

1： 建立axi/非axi工程，右键点击ddr-ip，选择输出xilinx官方仿真工程

2：打开该工程

3： 将官方仿真模型文件和sim_tb_top.v拷贝走

4：修改sim_tb_top.v文件，把自己ddr读写的工程加入，替代原xilinx的example_top。即可仿真

5：原有例子仅仅可以仿真1024个内存空间，如果需要更多，需要修改如下地方：

parameter MEM_BITS         =     23+5;// 15; // Set this parameter to control how many write data bursts can be stored in memory.  The default is 2^10=1024.

6：原官方例子，在一段时间后会停止，是因为原例子仅仅是ddr init成功后读写几次后停止。如果需要仿真时间更多，需要修改这里。

7：ok。

关于仿真出现很多Warning，很简单，vlog -suppress 2083，这些烦人的Warning就没有了。

“# ** Warning: (vlog-2083) ../ddr.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.v(641): Carriage return (0x0D) is not followed by a newline (0x0A).

# ** Warning: (vlog-2083) ../ddr.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.v(641): Carriage return (0x0D) is not followed by a newline (0x0A).

# ** Warning: (vlog-2083) ../ddr.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.v(653): Carriage return (0x0D) is not followed by a newline (0x0A).

# ** Warning: (vlog-2083) ../ddr.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.v(653): Carriage return (0x0D) is not followed by a newline (0x0A).

# ** Warning: (vlog-2083) ../ddr.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.v(653): Carriage return (0x0D) is not followed by a newline (0x0A).

# ** Warning: (vlog-2083) ../ddr.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.v(667): Carriage return (0x0D) is not followed by a newline (0x0A).

# ** Warning: (vlog-2083) ../ddr.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.v(667): Carriage return (0x0D) is not followed by a newline (0x0A).

# ** Warning: (vlog-2083) ../ddr.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig_sim.v(667): Carriage return (0x0D) is not follow"