第三课 MC9S08DZ60之通用输出输入GPIO

最新推荐文章于 2020-07-10 16:10:57 发布

DZWH

最新推荐文章于 2020-07-10 16:10:57 发布

阅读量1.9k

点赞数 1

分类专栏： MC9S08DZ60 MCU芯片驱动文章标签： Freescale MC9S08DZ60 Parallel I/O Driver MC

本文链接：https://blog.csdn.net/friendsdan/article/details/79493751

版权

对于初学单片机的读者，从第二课到第三课，应该会有种豁然开朗的感觉。对的，这节课讨论的是这款芯片的GPIO，很多课程老师用一句话：点亮一个LED灯。但是很不幸的告诉读者，这里不会真正的去点亮一个LED来展示。因为LED的点亮与熄灭，就是驱动单片机的GPIO口，输出高电平和低电平来进行控制，知道如何去设置寄存器，如何操作寄存器使I/O口输出期望的电平，是讲解的重点，本参考课程非常之简单。

1.请读者先阅读芯片资料中Chapter 6 Parallel Input/Output Control的6.1节和6.2节。

6.1节中记住的第一句话是：Reading and writing of parallel I/Os are performed through the port data registers. The direction, either input or output, is controlled through the port data direction registers.（读写并行I/O的操作都是由操作I/O端口数据寄存器来完成，I/O端口的方向,即输入或是输出，由I/O端口数据方向寄存器控制）很多大学生学过51单片机，玩的也很溜，也知道如何操作51单片机的I/O，甚至知晓通过硬件设计来拓展I/O资源。这里要说明下，MC8S08DZ60芯片，以及大部分8位16位和32位芯片，对I/O口的数据方向的控制由专门的数据方向寄存器控制，这点可能与51单片机不一样。

6.1节中第二句话：The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads。控制I/O数据方向的寄存器名为PTxDDn,x是不同类的并行I/O口，如PTA口、PTB口等，n为某一类并行口的一个控制位如PTADD1。

6.1节中第三句话：It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output.（改变端口数据方向前，写入安全的数据到端口数据寄存器）也就是确保单片器I/O初始化后端口数据状态的确定性。

6.2节中第一句话：An internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up enable register (PTxPEn).（芯片内部上拉设备，可以通过设置PTxPEn，来控制每一个I/O端口的上拉情况），另外需要注意！如果并行输入 / 输出控制逻辑或任何外围设备功能将管脚配置为输出，上拉器件就会被禁止，这与对应的上拉寄存器位的状态无关。如果管脚由模拟功能控制（也即I/O口被配置为其他功能口，而不是简单的I/O口），上拉器件同样会被禁止。

6.2节第二句话： When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions（该功能启动时，转换控制限制输出的转换速度，减少 EMC 发射）。斜率控制寄存器（PTxSEn）的设置可以减少EMC的发射，这个还是蛮重要的。另外如果管脚被配置为输出I/O，其设置不会产生任何影响。

6.2节还讲述了一个驱动强度寄存器PTxDSn，该寄存器的功能就是增加I/O管脚的输出和输入电流能力，但会影响到EMC。

2.看芯片管脚图，请读者找出芯片图中的所有的可用的I/O口。分别是PTA0-7、PTB0-7、PTC0-7、PTD0-7、PTE0-7、PTF0-7、PTG0-5，总共有54个管脚可配置为I/O口，其中PTG只有6个管脚。

3.作者要配置和使用的管脚及如何驱动。

工作内容，把PTC0~4管脚设置为输入口，把PTB0~7管脚设置为输入管脚，把PTG4管脚设置为输出，把PTD0~4管脚设置为输入，并操作它们的数据寄存器，进行数据输入和输出（高低电平获取和输出）。

原理图

4.代码部分

头文件H

#ifndef _DATA_TYPE_H_H
#define _DATA_TYPE_H_H

typedef char            INT8;
typedef unsigned char   UINT8;
typedef unsigned short  USHORT16;
typedef unsigned int    UNIT16;
typedef unsigned long   ULONG32;
typedef short           SHORT16;
typedef long            LONG32;
typedef unsigned char   BOOL;
#endif

#ifndef _GPIO_H_H
#define _GPIO_H_H
//------------------------------------------------------------------------------
/*PORTA管脚寄存器设置值和对应的移位量shift值*/
//A端口数据寄存器PTAD
//For port A pins that are inputs,reads return the logic level on the pin.
//For Port A pins this are configured as outputs,reads return the last value
//written to this register.
//表1-寄存器设置值-none 不需要
#define PTAD_RESET 0x00
//表2-移位量shift值
#define PTAD0 0
#define PTAD1 1
#define PTAD2 2
#define PTAD3 3
#define PTAD4 4
#define PTAD5 5
#define PTAD6 6
#define PTAD7 7
//A端口数据方向寄存器PTADD
//These read/write bits control the direction of port A pins and what is read 
//for PTAD reads.
//表1-寄存器设置值
#define PTADD_RESET 0x00
#define PTADD0_AS_INPUT  0x00
#define PTADD0_AS_OUTPUT 0x01
#define PTADD1_AS_INPUT  0x00
#define PTADD1_AS_OUTPUT 0x01
#define PTADD2_AS_INPUT  0x00
#define PTADD2_AS_OUTPUT 0x01
#define PTADD3_AS_INPUT  0x00
#define PTADD3_AS_OUTPUT 0x01
#define PTADD4_AS_INPUT  0x00
#define PTADD4_AS_OUTPUT 0x01
#define PTADD5_AS_INPUT  0x00
#define PTADD5_AS_OUTPUT 0x01
#define PTADD6_AS_INPUT  0x00
#define PTADD6_AS_OUTPUT 0x01
#define PTADD7_AS_INPUT  0x00
#define PTADD7_AS_OUTPUT 0x01
#define PTADD_AS_INPUT   0x00
#define PTADD_AS_OUTPUT  0xFF
//表2-移位量shift值
#define PTADD0 0
#define PTADD1 1
#define PTADD2 2
#define PTADD3 3
#define PTADD4 4
#define PTADD5 5
#define PTADD6 6
#define PTADD7 7
//A端口上拉使能寄存器PTAPE
//Each of these control bits determines if the internal pull-up or pull-down
//device is enabled for the associated PTA pin. For port A pins that are configured 
//as outputs, these bits have no effect and the internal pull devices are disabled.
//表1-寄存器设置值
#define PTAPE_RESET 0x00
#define PTAPE0_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTAPE0_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled.  
#define PTAPE1_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTAPE1_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled. 
#define PTAPE2_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTAPE2_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled. 
#define PTAPE3_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTAPE3_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled. 
#define PTAPE4_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTAPE4_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled. 
#define PTAPE5_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTAPE5_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled. 
#define PTAPE6_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTAPE6_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled. 
#define PTAPE7_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTAPE7_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled.
#define PTAPE_PULL_DISABLE  0x00 //Internal pull_up/pull_down of PTA all disabled.
#define PTAPE_PULL_ENABLE   0xFF //Internal pull_up/pull_down of PTA all enabled. 
//表2-移位量shift值
#define PTAPE0    0
#define PTAPE1    1
#define PTAPE2    2
#define PTAPE3    3
#define PTAPE4    4
#define PTAPE5    5
#define PTAPE6    6
#define PTAPE7    7
//A端口斜率使能寄存器
//Each of these control bits determines if the output slew rate control
//is enabled for the associated PTA pin. For port A pins that are configured as inputs, 
//these bits have no effect.
//表1-寄存器设置值
#define PTASE_RESET    0xFF
#define PTASE0_SLEW_RATE_DISABLE 0x00 //Output slew rate control disabled.
#define PTASE0_SLEW_RATE_ENABLE  0x01 //Output slew rate control enabled.
#define PTASE1_SLEW_RATE_DISABLE 0x00 //Output slew rate control disabled.
#define PTASE1_SLEW_RATE_ENABLE  0x01 //Output slew rate control enabled.
#define PTASE2_SLEW_RATE_DISABLE 0x00 //Output slew rate control disabled.
#define PTASE2_SLEW_RATE_ENABLE  0x01 //Output slew rate control enabled.
#define PTASE3_SLEW_RATE_DISABLE 0x00 //Output slew rate control disabled.
#define PTASE3_SLEW_RATE_ENABLE  0x01 //Output slew rate control enabled.
#define PTASE4_SLEW_RATE_DISABLE 0x00 //Output slew rate control disabled.
#define PTASE4_SLEW_RATE_ENABLE  0x01 //Output slew rate control enabled.
#define PTASE5_SLEW_RATE_DISABLE 0x00 //Output slew rate control disabled.
#define PTASE5_SLEW_RATE_ENABLE  0x01 //Output slew rate control enabled.
#define PTASE6_SLEW_RATE_DISABLE 0x00 //Output slew rate control disabled.
#define PTASE6_SLEW_RATE_ENABLE  0x01 //Output slew rate control enabled.
#define PTASE7_SLEW_RATE_DISABLE 0x00 //Output slew rate control disabled.
#define PTASE7_SLEW_RATE_ENABLE  0x01 //Output slew rate control enabled.
#define PTASE_SLEW_RATE_DISABLE  0x00 //Output slew rate control for PTA all disabled.
#define PTASE_SLEW_RATE_ENABLE   0xFF //Output slew rate control for PTA all enabled.
//表2-移位量shift值
#define PTASE0  0
#define PTASE1  1
#define PTASE2  2
#define PTASE3  3
#define PTASE4  4
#define PTASE5  5
#define PTASE6  6
#define PTASE7  7
//A端口驱动强度选择寄存器
//Each of these control bits selects between low and high
//output drive for the associated PTA pin. For port A pins that are configured 
//as inputs, these bits have no effect.
//表1-寄存器设置值
#define PTADS_RESET 0x00
#define PTADS0_LOW_STRENGTH  0x00 //Low output drive strength selected.
#define PTADS0_HIGH_STRENGTH  0x01 //High output drive strength selected.
#define PTADS1_LOW_STRENGTH  0x00 //Low output drive strength selected.
#define PTADS1_HIGH_STRENGTH  0x01 //High output drive strength selected.
#define PTADS2_LOW_STRENGTH  0x00 //Low output drive strength selected.
#define PTADS2_HIGH_STRENGTH  0x01 //High output drive strength selected.
#define PTADS3_LOW_STRENGTH  0x00 //Low output drive strength selected.
#define PTADS3_HIGH_STRENGTH  0x01 //High output drive strength selected.
#define PTADS4_LOW_STRENGTH  0x00 //Low output drive strength selected.
#define PTADS4_HIGH_STRENGTH  0x01 //High output drive strength selected.
#define PTADS5_LOW_STRENGTH  0x00 //Low output drive strength selected.
#define PTADS5_HIGH_STRENGTH  0x01 //High output drive strength selected.
#define PTADS6_LOW_STRENGTH  0x00 //Low output drive strength selected.
#define PTADS6_HIGH_STRENGTH  0x01 //High output drive strength selected.
#define PTADS7_LOW_STRENGTH  0x00 //Low output drive strength selected.
#define PTADS7_HIGH_STRENGTH  0x01 //High output drive strength selected.
#define PTADS_LOW_STRENGTH   0x00 //Low output drive strengh for all PTA.
#define PTADS_HIGH_STRENGTH   0x01 //High output driver strenggh for all PTA.
//表2-移位量shift值
#define PTADS0  0
#define PTADS1  1
#define PTADS2  2
#define PTADS3  3
#define PTADS4  4
#define PTADS5  5
#define PTADS6  6
#define PTADS7  7
//A端口中断状态控制寄存器PTASC

//表1-寄存器设置值
//None - configurations are in INTERRUPT mode
//表2-移位量shift值
//A端口中断管教选择寄存器PTAPS

//表1-寄存器设置值
//None - configurations are in INTERRUPT mode
//表2-移位量shift值
//A端口中断边沿选择寄存器PTAES

//表1-寄存器设置值
//None - configurations are in INTERRUPT mode
//表2-移位量shift值

//------------------------------------------------------------------------------
/*PORTB管脚寄存器设置值和对应的移位量shift值*/
//B端口数据寄存器PTBD
//For port B pins that are inputs,reads return the logic level on the pin.
//For Port B pins this are configured as outputs,reads return the last value
//written to this register.
//表1-寄存器设置值-none 不需要
#define PTBD_RESET 0x00
//表2-移位量shift值
#define PTBD0 0
#define PTBD1 1
#define PTBD2 2
#define PTBD3 3
#define PTBD4 4
#define PTBD5 5
#define PTBD6 6
#define PTBD7 7
//B端口数据方向寄存器PTBDD
//These read/write bits control the direction of port B pins and what is read 
//for PTBD reads.
//表1-寄存器设置值
#define PTBDD_RESET 0x00
#define PTBDD0_AS_INPUT  0x00
#define PTBDD0_AS_OUTPUT 0x01
#define PTBDD1_AS_INPUT  0x00
#define PTBDD1_AS_OUTPUT 0x01
#define PTBDD2_AS_INPUT  0x00
#define PTBDD2_AS_OUTPUT 0x01
#define PTBDD3_AS_INPUT  0x00
#define PTBDD3_AS_OUTPUT 0x01
#define PTBDD4_AS_INPUT  0x00
#define PTBDD4_AS_OUTPUT 0x01
#define PTBDD5_AS_INPUT  0x00
#define PTBDD5_AS_OUTPUT 0x01
#define PTBDD6_AS_INPUT  0x00
#define PTBDD6_AS_OUTPUT 0x01
#define PTBDD7_AS_INPUT  0x00
#define PTBDD7_AS_OUTPUT 0x01
#define PTBDD_AS_INPUT   0x00
#define PTBDD_AS_OUTPUT  0xFF
//表2-移位量shift值
#define PTBDD0 0
#define PTBDD1 1
#define PTBDD2 2
#define PTBDD3 3
#define PTBDD4 4
#define PTBDD5 5
#define PTBDD6 6
#define PTBDD7 7
//B端口上拉使能寄存器PTBPE
//Each of these control bits determines if the internal pull-up or pull-down
//device is enabled for the associated PTB pin. For port B pins that are configured 
//as outputs, these bits have no effect and the internal pull devices are disabled.
//表1-寄存器设置值
#define PTBPE_RESET 0x00
#define PTBPE0_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTBPE0_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled.  
#define PTBPE1_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTBPE1_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled. 
#define PTBPE2_PULL_DISABLE 0x00 //Internal pull_up/pull_down device disabled.
#define PTBPE2_PULL_ENABLE  0x01 //Internal pull_up/pull_down device enabled. 
#define PTBPE3_PULL_DISA

最低0.47元/天解锁文章

DZWH

关注

1
点赞
踩
11

收藏

觉得还不错? 一键收藏
0
评论
第三课 MC9S08DZ60之通用输出输入GPIO

对于初学单片机的读者，从第二课到第三课，应该会有种豁然开朗的感觉。对的，这节课讨论的是这款芯片的GPIO，很多课程老师用一句话：点亮一个LED灯。但是很不幸的告诉读者，这里不会真正的去点亮一个LED来展示。因为LED的点亮与熄灭，就是驱动单片机的GPIO口，输出高电平和低电平来进行控制，知道如何去设置寄存器，如何操作寄存器使I/O口输出期望的电平，是讲解的重点，本参考课程非常之简单。1.请读者先阅...
复制链接

扫一扫