Gr1x's Blog

1. To maximize signal integrity, the use of controlled impedance traces of Z0 = 50 ohms (±10%) characteristic impedance should be considered.   2. Consider routing high frequency signals on layers adj

CURRENT consumption is constantly rising with increasing clock frequencies in modern VLSI circuits. The Power Delivery Network (PDN) is required to have a low-impedance resonant-free profile over a w

Q:    Recently, Im going to layout a board which has a 200 pin SO-DIMM DDR slot, a DDR 333 memory module will be plugged in. Now, I wanna to simulate the data/command/control signals of the DDR trace

说到IC Design就离不开EDA TOOLS。IC设计中EDA工具的日臻完善已经使工程师完全摆脱了原先手工操作的蒙昧期。IC设计向来就是EDA工具和人脑的结合。随着IC不断向高集成度、高速度、低功耗、高性能发展，没有高可靠性的计算机辅助设计手段，完成设计是不可能的。IC 设计的EDA工具真正起步于80年代，1983年诞生了第一台工作站平台apollo；20年的发展，从硬件描述语言（或是图形输入

DDR does requirecleaner reference signals, reduced setup and hold times, and matchedsignal lengths to reduce signal skew effects.Vrefshould be isolated from other nets, decoupled from both

General layout Guidelines1. Diode/LED footprint needs to have polarity. The symbol of the diode can be present inside the outline.2.Positive polarity for tantalum and electrolytic capacitors nee

 DDR2 ROUTING GUIDELINES:  All signals from the FPGA to DDR2 modules and to the VTTtermination resistors are 50-ohm transmission lines referenced to theground planes.The ground planes mu