DDR Layout constraint

1. To maximize signal integrity, the use of controlled impedance traces of Z0 = 50 ohms (±10%) characteristic impedance should be considered.  
2. Consider routing high frequency signals on layers adjacent to a common reference plane (i.e. power or ground). 
3. Route each data group (DQS and DQ) on the same layer to match propagation delays and minimize skew. 
4. Route similar signals (i.e. address bus or data bus) on the same layer to match propagation delays and minimize signal –signal skew.
5. Separate low frequency and high frequency signals to minimize crosstalk.
6. Traces should be routed in a daisy chain manner versus a star topology to maintain signal integrity and facilitate a termination connection (if required).
7. Maximize trace spacing to other signal groups:
8. Signals should be routed in a daisy chain topology and preferably on the same layer with no vias.
9. When connecting two or more memories, make the DDR address and control signals about the same length as the DDR clock traces. This will ensure the data setup and hold times are met.
10. To minimize potential timing issues induced by trace routing. The DQ[63:0] and associated DQS[7:0] should have equal trace lengths. The data bus and data strobe should be matched in groups.
11. Use IBIS models and simulation tools to ensure the setup and hold times are met at maximum operating frequency of the DDR SDRAM.

The SSTL_2 I/O standard for DDR SDRAM uses a reference voltage to maintain the DDR signals near their switching levels to increase switching speed.The VREF signal can be generated using a simple resistor divider with 1% or better accuracy.

The VREF voltage signal should meet the following requirements to ensure maximum DDR SDRAM performance:
• Maintain maximum clearance from other nets
• Use a distributed decoupling scheme to minimize ESL and localize transient currents and returns.
• Simplify interface by routing on the top signal trace layer.

The termination voltage supply (VTT) needs to track the DDR SDRAM supply voltage, VDDQ, and it needs to source and sink the load current. Here are some guidelines for VTT layout and implementation:
• Place termination resistors on a top layer VTT (termination voltage supply) which is at the end of the bus.
• Place the VTT generator as close as possible to the termination resistors.
• Its maximum voltage deviation should not exceed 40mV during extreme load transients, from the maximum rated sinking current to the maximum rated sourcing current.