Lab Notes : Altera UniPHY for DDR and QDR

Link outside GFW

http://hax4.blogspot.com/2011/05/lab-notes-altera-uniphy-for-ddr-and-qdr.html

Altera provides UniPHY megafunction for DDR and QDR respectively. If you use them in your FPGA design, here are a few words for caution:

(1) The UniPHY needs Pull up and Pull down resistor for OCT calibration. Make sure these resistors are in place. (Usually 50 ohm 1%)

(2) assign pin locations.

(3) Copy timing parameters, such as tSA etc, from datasheet to the mem parameters tab during megafunction setup. Set up other things accordingly.

(4) Provide your base clock (oscillator) to pin pll_ref_clk. Make sure pll_locked is asserted after reset

(5) The UniPHY has a calibration process during initialization. Make sure the afi_cal_success signal is asserted after reset

(6) Often times, the calibration process fails. (afi_cal_fail is raised.). Other than the board problem, the usual suspecter is that the design is not properly constrained. In Quartus II, please run the TCL script called xxx_pin_assignments.tcl from the mega-plugin generated folder.

(7) For QDR, the chip usually needs two clocks. One is the K, the other is the C. If the QDR SRAM is not in single clock mode, C is needed. However, the UniPHY does not provide C on its memory interface. One way to generate the C is to use an obuf that is based on the pll_mem_clk.

(8) The difference between QDR and DDR is that the former is dual port while the latter in single port. i.e, DDR bus is bi-directional. To deal with signal integrity issues, ODT can be enabled on DDR chips.

(9) BTW, Qsys fantastic. Although you don't have to use Qsys, Qsys is a great way to connect processor to the DDR/QDR