Lab Notes: Altera PFL

Link outside GFW

http://hax4.blogspot.com/2011/05/lab-notes-altera-pfl.html

One way to config Altera FPGA is to use an Altera CPLD as flash controller; read out the FPGA bit file from flash and config the FPGA device during power on. The CPLD could also function as a flash programmer through its JTAG interface.

Altera has a megafunction called PFL (Parallel Flash Loader) in its Quartus II software. Here are a few notes on PFL:

(1) Prepare the FPGA image. The default file format generated by Quartus II is .sof format. It should be converted by Quartus II (under Menu File) to .pof format

(2) PFL has both programmer and loader function. Please be advised that if "optimization for speed" is chosen, the size of this megafunction could be pretty big for some MAX II device.

(3) Under Quartu II programmer software, right click the CPLD device and choose "attach flash device" to add a flash attachment. Add the flash device and .pof file from there.

(4) It might take more than 10 minutes to program a big flash. And more than 30 minutes to verify the flash.

(5) When program the flash through CPLD's JTAG, sometimes it will show "Can't recognize silicon ID for device x". Other than the board problem, it is usually the incorrect IO constrain on CPLD that leads to such failure. (Please note that flash_data[] is bidirectional. pfl_flash_access_granted can be set to high, and leave pfl_flash_access_request unconnected)