现代X86汇编-第一章-X86-64核心架构

昨天本来还要再用vs2022写一个例子，发现.386, .plat,c 甚至函数压栈的push ebp都编译不过，只有附录A的AVX特性的例子过了，才了解到X64已经和以前的32位win32程序有很大不同，需要老老实实的从第一章重新建立新的64位知识体系。

let'go chapter 1: X86-64 Core Architecture

历史：CPU发展史，包括intel,amd两个巨头

• 1985年的80386是第一个32位处理器
• SIMD  a single instruction that concurrently manipulates multiple data values 1993 the first Pentium
• Streaming SIMD Extensions (SSE)，1999年，The Pentium III
• 2011年，新一代SIMD技术，Advanced Vector Extensions (AVX).using 256-bit wide registers and operands.
• 2013年，Haswell microarchitecture. Haswell includes AVX2
• 2003年，AMD推出Opteron processor, which extended the x86’s execution environment from 32 bits to 64 bits。这个是比intel早，所以64位平台叫做AMD64,谁早谁就有冠名权。
• 2004年，intel才姗姗来迟，Pentium 4.
• 2017年，Intel’s Skylake-X microarchitecture，a new SIMD extension called AVX-512，using 512-bit wide registers and operands。

数据类型

基本数据类型：fundamental data type: ranging from 8 bits to 128 bits.

数字类型：Numerical Data Types:

• char 8
• short 16
• int,long(windows) 32
• long(Linux),long long 64
• float 32
• double 64

请注意 C++ long 和 unsigned long 的大小不同。Linux 的64 位版本使用 64 位宽整数表示 long 和 unsigned long，而 Windows 的64 位版本则使用 32 位宽整数表示这些类型。

x86-64 Processor Architecture

寄存器变化很大,寄存器数量大幅增加了，intel少寄存器的时代结束了。应该是收到了ARM结构影响。
通用寄存器General Purpose Registers
contain 16 64-bit wide general-purpose registers.

• RAX,RBX,RCX,RDX
• RSI,RDI
• RBP,RSP
• R8,R9,R10,R11,R12,R13,R14,R15

指针 Instruction Pointer

• RIP

RFLAGS Register
Floating-Point and SIMD Registers
AVX and AVX2 include 16 256-bit wide registers named YMM0-YMM15.
The low-order 128 bits of each YMM register is aliased to a 128-bit wide XMM
register.
AVX-512 extends the width of each YMM register from 256 bits to 512 bits.
The 512-bit wide registers are named ZMM0-ZMM15.
AVX-512 also adds 16 new SIMD registers named ZMM16-ZMM31.
MXCSR Register
All X86-64 processors include a 32-bit control-status register named MXCSR.
 

Instruction Operands
There are three basic types of operands: immediate, register, and memory.
Immediate:
mov rax,42    rax = 42
imul r12,-47  r12 *= -47
shl r15,8     r15 <<= 8
xor ecx,80000000h ecx ^= 0x80000000
sub r9b,14    r9b -= 14
Register:
mov rax,rbx  rax = rbx
add rbx,r10  rbx += r10
mul rbx      rdx:rax = rax * rbx
and r8w,0ff00h r8w &= 0xff00
Memory:
mov rax,[r13]  rax = *r13
or rcx,[rbx+rsi*8] rcx |= *(rbx+rsi*8)
mov qword ptr [r8],17  *(long long*)r8 = 17
shl word [r12],2   *(short*)r12 <<= 2
 

The mul rbx (Multiply Unsigned Integers) instruction that is shown in Table
1-6 is an example of an instruction that uses an implicit operand.
In this example, implicit register RAX and explicit register RBX are used as
the source operands, and implicit register pair RDX:RAX is the destination
operand. The multiplicative product's high-order and low-order quawords are
stored in RDX and RAX,respectively.
 

The text qword ptr that's used in Table 1-6's penultimate example is a MASM
size operator that acts like a C++ cast operator.
In this instruction, 17 is subtracted from the 64-bit value whose memory
location is specified by the contents of register R8. Without the qword ptr
size operator, the assembly language statement is ambiguous since the
assembler cannot ascertain the size of the operand pointed to by R8;

Memory Addressing
An x86 instruction requires up to four separate components to specify the
location of an operand in memory.
EffectiveAddress = BaseReg + IndexReg * ScaleFactor + Disp
RIP+Disp      mov rax,[Val]
BaseReg       mov rax,[rbx]
BaseReg+Disp  mov rax,[rbx+16]
IndexReg*SF+Disp mov rax,[r15*8+48]
BaseReg+IndexReg mov rax,[rbx+r15]
BaseReg+IndexReg+Disp mov rax,[rbx+r15+32]
BaseReg+IndexReg*SF   mov rax,[rbx+r15*8]
BaseReg+IndexReg*SF+Disp mov rax,[rbx+r15*8+64]
 

Condition Codes--这部分没有讲明白
Most x86-64 arithmetic,bitwise logical,shift,and rotate instructions update
one or more of th status flags in the RFLAGS register.
As discussed earlier in this chapter, the status flags provide additional
information about the results of an operation. The jcc, cmovecc(Conditional
Move), and setcc(Set Byte on Condition) instructions use what are called
condition codes to test the status flags either individually or logically
combined.
 

Differences Between X86-64 and X86-32
add al,bl add ax,bx add eax,ebx add rax,rbx
cmp dl,[r15] cmp dx,[r15] cmp edx,[r15] cmp rdx,[r15]
mul r10b mul r10w mul r10d mul r10
or [r8+rdi],al or [r8+rdi],ax or [r8+rdi],eax or [r8+rdi],rax
shl r9b,cl shl r9w,cl  shl r9d,cl shl r9,cl