Error (11802): Can‘t fit design in device. Modify your design to reduce resources, or choose a large

在quartus prime18.1中的报错 
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

//设备支持不了，所以不再往下写了。
//解决这个问题了，出现这个问题的原因是顶层模块接口，超过了288个，我删除掉几个测试接口就好了

如下是我报错的顶层模块代码，可以看到输出的I/O端口正好是289个

module network30(
input wire [31:0]x,
input wire clk,
output wire [31:0]result,
output wire [31:0]a1_in_out,a1_in_out1,a1_in_out29,
output wire [31:0]a1_out,a1_out1,a1_out29,
output wire [31:0]xp1_out
);

如下是我修改过后的代码，我把测试用的I/O端口注释掉就好了

module network30(
input wire [31:0]x,
input wire clk,
output wire [31:0]result,
//output wire [31:0]a1_in_out,a1_in_out1,a1_in_out29,
output wire [31:0]a1_out,a1_out1,a1_out29,
output wire [31:0]xp1_out
);