Recovery Slave PR00 previously exited with exception 10459

单实例搭建RAC 备库,备库的两个节点都mount后,启动日志应用,报下下面的错误:
 

alter database recover managed standby database using current logfile disconnect;
Errors in file /oracle/database/diag/rdbms/bpmrac/bpmrac01/trace/bpmrac01_pr00_54583.trc:
ORA-10459: cannot start media recovery on standby database; conflicting state detected
Managed Standby Recovery not using Real Time Apply
Recovery Slave PR00 previously exited with exception 10459
MRP0: Background Media Recovery process shutdown (bpmrac01)

查看该错误的解释:

-bash: ora: command not found
[oracle@bpmrac01 trace]$ oerr ora 10459
10459, 00000, "cannot start media recovery on standby database; conflicting state detected"
// *Cause:  An attempt was made to perform media recovery on a standby
//          database while another instance was performing recovery on
//          the standby database, had the standby database open, or a data file
//          move operation was in progress.
// *Action: Close the standby on all other instances, cancel any conflicting
//          recovery session or data file move operation, and perform manual
//          recovery.
//

从解释中看到 关闭其他实例的字眼 ,这样情况是不是备库只能启动一个实例呢?那就把另外一个节点关闭,在启动日志应用进进程,发现没有报错了 

srvctl stop  instance -d bpmrac   -i  bpmrac02 

 

An AXI slave with outstanding transactions can be implemented in Verilog by using a state machine to manage the response to incoming transactions. The state machine can keep track of the number of outstanding transactions and respond accordingly. Here is an example implementation: ``` module axi_slave_outstanding( input aclk, input aresetn, input awvalid, input [31:0] awaddr, input [2:0] awprot, input awcache, input awburst, input [3:0] awlen, input arvalid, input [31:0] araddr, input [2:0] arprot, input arcache, input arburst, input [3:0] arlen, input wvalid, input [31:0] wdata, input [3:0] wstrb, input wlast, output bvalid, output rvalid, output [1:0] rresp, output [31:0] rdata, output rlast ); reg [1:0] state; reg [31:0] mem[0:1023]; reg [3:0] arcount; reg [3:0] awcount; // Reset state machine and counters on reset always @(posedge aclk) begin if (!aresetn) begin state <= 2'b00; arcount <= 4'b0000; awcount <= 4'b0000; end end // State machine always @(posedge aclk) begin case (state) // Idle state 2'b00: begin if (awvalid) begin state <= 2'b01; awcount <= awlen; end else if (arvalid) begin state <= 2'b10; arcount <= arlen; end end // Write data state 2'b01: begin if (wvalid) begin mem[awaddr] <= wdata; awaddr <= awaddr + 1; awcount <= awcount - 1; if (wlast) begin bvalid <= 1'b1; state <= 2'b00; end end end // Read data state 2'b10: begin if (rcount == 4'b0000) begin rvalid <= 1'b1; rdata <= mem[araddr]; end araddr <= araddr + 1; arcount <= arcount - 1; if (arcount == 4'b0000) begin rlast <= 1'b1; rvalid <= 1'b0; state <= 2'b00; end end // Error state default: begin state <= 2'b00; end endcase end endmodule ``` In this implementation, the state machine has three states: idle, write data, and read data. When an AXI write transaction is received, the state machine transitions to the write data state and writes the incoming data to memory. It also keeps track of the number of outstanding write transactions using the `awcount` counter. When an AXI read transaction is received, the state machine transitions to the read data state and reads the requested data from memory. It also keeps track of the number of outstanding read transactions using the `arcount` counter. The `bvalid`, `rvalid`, `rdata`, and `rlast` outputs are used to signal the completion of the AXI transactions to the master. The `bvalid` output is set to 1 when a write response is ready, and the `rvalid` output is set to 1 when a read response is ready. The `rdata` output contains the read data, and the `rlast` output signals the end of a read transaction. This implementation assumes a single master and a single slave, and does not support burst transactions or interleaved transactions. It also does not support any AXI extensions beyond the basic read and write transactions.
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