HDLBits刷题记录——fancytimer

导言

定时器是和实际应用很贴近的一道题目。而且我曾在EDA课上做过类似的PJ，可惜当时从未接触过硬件描述语言，最终并没有得到一个正确的时钟计数器。

思路

• 前面四题（HDLBits<Circuitd<Biulding larger circuits）正是这个complete timer的铺垫
  • 序列检测状态机
  • 移位操作状态机
  • 下行计数器
• 后面一题用独热码的方式表示状态的转移。我对独热码的理解还有待加强，关键在于：
  • 状态的表示方式是：state中某一位为高，即进入该位代表的状态
  • 下一状态同样取决于当前状态和输入值，注意当前状态是用单bit数表示的

代码

常见状态编码：

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    
    parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8,S9=9;
    reg [3:0] state,next,delay;
    reg [9:0] down;
    wire shift_ena,done_counting;
    
    assign count = delay;
    assign done_counting = (count == 4'd0 && down == 10'd999);
    
    always@(posedge clk) begin
        if(reset) begin
            state <= S0;
        end
        else begin
            state <= next;
        end
    end
    
    always@* begin
        case(state)
            S0: next = data ? S1:S0;
            S1: next = data ? S2:S0;
            S2: next = data ? S2:S3;
            S3: next = data ? S4:S0;
            S4: next = S5;
            S5: next = S6;
            S6: next = S7;
            S7: next = S8;
            S8: next = done_counting ? S9:S8;
            S9: next = ack ? S0:S9;
            default: next = S0;
        endcase
    end
    
    //shfit in delay cycle
    always@(posedge clk) begin
        if(reset) begin
            shift_ena <= 1'b0;
        end
        else if(next == S4 || next == S5 || next == S6 || next == S7) begin
            shift_ena <= 1'b1;
        end
        else begin
            shift_ena <= 1'b0;
        end
    end
    
    always@(posedge clk) begin
        if(reset) begin
            delay <= 4'b0;
        end
        else if(shift_ena) begin
            delay <= {delay[2:0],data};
        end
        else if(down == 10'd999) begin
            delay <= delay - 1'b1;
        end
        else begin
            delay <= delay;
        end
    end
      
    // counting down from setting number
    always@(posedge clk) begin
        if(reset) begin
            counting <= 1'b0;
        end
        else if(next == S8) begin
            counting <= 1'b1;
        end
        else begin
            counting <= 1'b0;
        end
    end 
    
       
    always@(posedge clk) begin
        if(reset) begin
            down <= 10'd0;
        end
        else if(counting) begin
            if(down == 10'd999) begin
                down <= 10'd0;
            end
            else begin
                down <= down + 1'b1;
            end
        end
        else begin
        	down <= down;
        end
    end            
    
    always@(posedge clk) begin
        if(reset) begin
            done <= 1'b0;
        end
        else if(next == S9) begin
            done <= 1'b1;
        end
        else begin
            done <= 1'b0;
        end
    end 

endmodule

独热码状态机：

• 做题小技巧：看指向下一状态的箭头都来自于哪里。比如，S_next的下一状态（即S下一时刻是1还是0）是S1\S11\S110\WaitAND其对应输入后再OR的结果。

module top_module(
    input d,
    input done_counting,
    input ack,
    input [9:0] state,    // 10-bit one-hot current state
    output B3_next,
    output S_next,
    output S1_next,
    output Count_next,
    output Wait_next,
    output done,
    output counting,
    output shift_ena
); //

    // You may use these parameters to access state bits using e.g., state[B2] instead of state[6].
    parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9;

    assign B3_next = state[B2];
    assign S_next = (state[S] & ~d | state[S1] & ~d | state[S110] & ~d | state[Wait] & ack);
    assign S1_next = (state[S] & d);
    assign Count_next = (state[Count] & ~done_counting | state[B3]);
    assign Wait_next = (state[Count] & done_counting | state[Wait] & ~ack);
    
    assign done = state[Wait];
    assign counting = state[Count];
    assign shift_ena = (state[B0] | state[B1] | state[B2] | state[B3]);   

endmodule

总结

做电路不是写代码。我明显感受到，当我把题意读清楚以后，在状态图和时序图的帮助下，写代码相对来说简单了许多。所以电路设计难在设计，而非代码。