2440notes

OM1-2  00 nand flash mode equen
 01 16bit
 10 32bit
 11 test mode

k4s561632 256Mbit 32MBytes

k4S561632A
.JEDEC standard 3.3V power support
.LVTTL compatible with multiplexed address
.Four banks operation
.MRS cycle with address key programs(Mode register setting)
-.CAS latency(2 & 3)
-.Burst length(1,2,4,8&Full pages)
-.Burst type(Squential &interleave)
.all inputs are sampled at the positive going edge of the system clock
.burst read single-bit write operation
.DQM for masking
.auto & self refresh
.64ms refresh period(8k Cycle)

main pin in k4s561632
clk
link to SCLK1:0
cke
link to SCKE

CS
Chip select:Disables or enables device operation by masking or enabling all inputs except CLK,CKE and DQE
link to 2440a LnGCS6 ->bank6
BA0~BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
link to 2440a LAddr[20:21]
RAS
Row address strobe
Enables row access & precharge
link to nSRAD
CAS
Column address strobe
Enables column access
link to nSCAS

WE
Write enable
Enables write operation and row precharge
Latches data in starting from CAS,WE active.
L(U)DQM
Data input/output mask
two chip link to LnWBE[3:0]

attention pins not used in 2440a
nOE-nOE(Output Enable) indicated that the current bus cycle is a read cycle
nSCS[1:0]SDRAM chip select
nBE[3:0] Upper byte/lower byte enable(in case of 16-bit SRAM)
DQM[3:0] SDRAM data mask

nwait pin operation
If the WAIT bit(WSn bit in BWSCON) corresponding to each memory bank is enabled,the nOE duration should be prolonged by external nWAIT pin while the memory is active.nWAIT is checked from tacc-1.nOE will be de-asserted at the next clock after sampling nWAIT is hign.The nWE signal have the same relation with nOE.

register

BWSCON 0x48000000 bus width &wait status control register
St7 0 WS7 0 DW7 00
ST6 0 WS6 0 DW6 10

BANKCONn:
BANKCON0-0x48000004 Bank 0 control register
BANKCON1-0x48000008 Bank 1 control register
BANKCON2-0x4800000C Bank 2 control register
BANKCON3-0x48000010 Bank 3 control register
BANKCON4-0x48000014 Bank 4 control register
BANKCON5-0x48000018 Bank 5 control register

Tacs[14:13]  address set-up time before nGCSn
Tcos[12:11]  chip selection set-up time before nOE
Tacc[10:8]  Access cycle
Tcoh[7:6] Chip selection hold time after nOE
Tcah[5:4] Address hold time after nOE
Tacp[3:2] Page mode access cycle@Page mode
PMC  Page mode configuration
BWSCON   0x48000000           R/W Bus Width & Wait Status Control
BANKCON6 0x4800001C         BANK6 Control
BANKCON7 0x48000020         BANK7 Control
REFRESH 0x48000024           DRAM/SDRAM Refresh Control
BANKSIZE 0x48000028           Flexible Bank Size
MRSRB6   0x4800002C           Mode register set for SDRAM BANK6
MRSRB7   0x48000030           Mode register set for SDRAM BANK7