串口初始化及读写

最新推荐文章于 2024-06-29 11:06:13 发布

lf12345678910

最新推荐文章于 2024-06-29 11:06:13 发布

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分类专栏： Android 驱动

本文链接：https://blog.csdn.net/lf12345678910/article/details/102514358

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本文档详细介绍了MTK平台下UART（通用异步收发传输器）的初始化过程，包括模块注册、串口设备注册、时钟配置、中断处理等，并展示了读写操作的实现细节，如串口中断处理函数`mtk_uart_irq`中的`mtk_uart_tx_handler`和`mtk_uart_rx_handler`。内容涉及了UART0和UART1的初始化及其在不同场景下的工作模式设置，如串口睡眠模式`mtk_uart_enable_sleep`，以及波特率的设置。此外，还涵盖了串口与设备树`mt6739.dtsi`中相关节点的配置。

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kernel-4.4\drivers\misc\mediatek\uart\uart.c
module_init(mtk_uart_init);
module_exit(mtk_uart_exit);

一、注册串口设备
mtk_uart_init
[UART0]
mtk_uart_probe
   err = clk_prepare(uart_setting->clk_uart_main);//[name:uart&][UART0][CCF]clk_uart_main:ffffffc01cf2f180
   err = clk_prepare(clk_uart0_dma);//[name:uart&][UART][CCF]clk_uart0_dma:ffffffc01cf2fd80
   set_uart_dma_clk(pdev->id, clk_uart0_dma);//[name:platform_uart&][UART0][CCF]enabled clk_uart_dma:ffffffc01cf2fd80
   set_uart_pinctrl(pdev->id, ppinctrl);//[name:platform_uart&][UART0][CCF]set_uart_pinctrl(0,ffffffc01cf2fc00), UART_NR:2
   pr_debug("[UART%d][PinC]set idx:%d, ppinctrl:%p\n", pdev->id, pdev->id, ppinctrl);//[name:uart&][UART0][PinC]set idx:0, ppinctrl:ffffffc01cf2fc00
   err = uart_add_one_port(&mtk_uart_drv, &uart->port);
       uart_configure_port(drv, state, uport);
           uart_report_port(drv, port);
               printk(KERN_INFO "%s%s%s%d at %s (irq = %d, base_baud = %d) is a %s\n",port->dev ? dev_name(port->dev) : "",port->dev ? ": " : "",drv->dev_name,drv->tty_driver->name_base + port->line,address, port->irq, port->uartclk / 16, uart_type(port));//11002000.apuart0: ttyMT0 at MMIO 0x0 (irq = 6, base_baud = 1625000) is a MTK UART

[ 3.338429] -(2)[1:swapper/0]Call trace:
[ 3.338443] -(2)[1:swapper/0][<ffffff800808acd0>] dump_backtrace+0x0/0x1d4
[ 3.338469] -(2)[1:swapper/0][<ffffff800808affc>] show_stack+0x14/0x1c
[ 3.338489] -(2)[1:swapper/0][<ffffff800838011c>] dump_stack+0xa8/0xe0
[ 3.338508] -(2)[1:swapper/0][<ffffff8008497258>] mtk_uart_power_up+0xe0/0x220
[ 3.338530] -(2)[1:swapper/0][<ffffff80084930ec>] mtk_uart_power_mgnt+0x78/0xd4
[ 3.338550] -(2)[1:swapper/0][<ffffff80083e3ebc>] uart_change_pm+0x38/0x48
[ 3.338570] -(2)[1:swapper/0][<ffffff80083e60f0>] uart_add_one_port+0x2c0/0x420
[ 3.338589] -(2)[1:swapper/0][<ffffff800849410c>] mtk_uart_probe+0x454/0x4cc
[ 3.338609] -(2)[1:swapper/0][<ffffff8008425ea0>] platform_drv_probe+0x58/0xa4
[ 3.338630] -(2)[1:swapper/0][<ffffff8008423bb4>] driver_probe_device+0x1f0/0x45c
[ 3.338649] -(2)[1:swapper/0][<ffffff8008423e8c>] __driver_attach+0x6c/0x98
[ 3.338668] -(2)[1:swapper/0][<ffffff80084228f0>] bus_for_each_dev+0x80/0xb0
[ 3.338687] -(2)[1:swapper/0][<ffffff8008423530>] driver_attach+0x20/0x28
[ 3.338705] -(2)[1:swapper/0][<ffffff800842303c>] bus_add_driver+0x13c/0x24c
[ 3.338722] -(2)[1:swapper/0][<ffffff8008424d68>] driver_register+0x94/0xe0
[ 3.338740] -(2)[1:swapper/0][<ffffff8008425dbc>] __platform_driver_register+0x48/0x50
[ 3.338759] -(2)[1:swapper/0][<ffffff8009466c98>] mtk_uart_init+0x98/0xec
[ 3.338778] -(2)[1:swapper/0][<ffffff8008082b68>] do_one_initcall+0xf8/0x1dc
[ 3.338797] -(2)[1:swapper/0][<ffffff8009431d74>] kernel_init_freeable+0x204/0x2ec
[ 3.338818] -(2)[1:swapper/0][<ffffff8008d27934>] kernel_init+0x14/0x164
[ 3.338840] -(2)[1:swapper/0][<ffffff8008085f90>] ret_from_fork+0x10/0x40

           /* Power up port for set_mctrl() */
           uart_change_pm(state, UART_PM_STATE_ON);
               uart_change_pm
                   port->ops->pm(port, pm_state, state->pm_state);//static const struct uart_ops mtk_uart_ops = {.pm = mtk_uart_power_mgnt,};
                       mtk_uart_power_mgnt
                           mtk_uart_power_up(uart);
                               pr_debug("[UART%d][CCF]enabled clk_uart_main:%p\n", uart->nport,
                                   setting->clk_uart_main);

   err = mtk_uart_vfifo_create(uart);//[name:uart&][UART 0] create
   MSG_RAW("[%2d] %p (%04d) ;\n", idx, vfifo->addr, vfifo->size);//[name:uart&][ 0] ffffff800ae83000 (1024) ;//[name:uart&][ 1] ffffff800ae84000 (1024) ;

kernel-4.4\arch\arm64\boot\dts\mediatek\mt6739.dtsi
   apuart0: apuart0@11002000 {
       cell-index = <0>;
       compatible = "mediatek,mtk-uart";
       reg = <0 0x11002000 0 0x1000>, /* UART0 base. */
           <0 0x11000600 0 0x80>, /* DMA Tx base. */
           <0 0x11000680 0 0x80>; /* DMA Rx base. */
       interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
       clock-frequency = <26000000>;
       clock-div = <1>;
       clocks = <&infracfg_ao CLK_INFRA_UART0>, <&infracfg_ao CLK_INFRA_AP_DMA>;
       clock-names = "uart0-main",