Shared buses vs NoCs

Noc(Network onchip )

-Each integrated IP core adds bus load capacitance

+Only point-to-point one-way links are used

 

-Bus timing problems in deep sub-micron designs

+Better suited for GALS paradigm

 

-Arbiter delay grows with no of masters. Instance-specific arbiter

+Distributed routing decisions. Reinstantiable switches

 

-Bus bandwidth is shared among all masters

+Bus bandwidth scales with network dimension

 

+After bus is granted, bus access latency is null

-Unpredictable latency due to network congestion problems

 

+Very low silicon cost

-High area cost

 

+Simple bus-IP core interface

-Network-IP core interface can be very complex (e.g. packetization,..)

 

+Design guidelines are well known

-New design paradigm