STM32F030C8 使用内部振荡器

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最新推荐文章于 2024-07-25 21:17:05 发布

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分类专栏：笔记文章标签： stm32 arm

原文链接：https://blog.csdn.net/xia_xia_mg/article/details/118764159

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system_stm32f0xx.c

/**
******************************************************************************
* @file stm32f0xx_
* @author MCD Application Team
* @version V1.3.0
* @date 16-January-2014
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and Configuration
* + Power saving
* + Analog Watchdog configuration
* + Temperature Sensor, Vrefint (Internal Reference Voltage) and
* Vbat (Voltage battery) management
* + ADC Channels Configuration
* + ADC Channels DMA Configuration
* + Interrupts and flags management
*
* @verbatim
================================================================================


/**
  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
  *         settings.
  * @note   This function should be called only once the RCC clock configuration
  *         is reset to the default reset state (done in SystemInit() function).
  * @param  None
  * @retval None
  */
static void SetSysClock(void)
{
		__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
  
  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
#if defined (PLL_SOURCE_HSI)
 
	//Enable HSI
	RCC->CR |= RCC_CR_HSION;
	//Wait till Hsi is ready	
	do
  {
   HSIStatus = RCC->CR & RCC_CR_HSIRDY;
    StartUpCounter++;  
  } while((HSIStatus== 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
	 if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
  {
		HSIStatus = (uint32_t)0x01;
  }
  else  
  {
		HSIStatus = (uint32_t)0x00;
  }  
	if(HSIStatus==(uint32_t)0x01)
	{
		/* Enable Prefetch Buffer and set Flash Latency */
		FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
				//Set AHB prescaler /1  48M
		RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
		//Set APB prescaler /1 48M
		RCC->CFGR |= RCC_CFGR_PPRE_DIV1;
		
		 /* PLL configuration = HSI/2 * 12= 48 MHz */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL));
		
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL12); //RC时钟2分频后 进行12倍频</font>
		
		
//		//Select Pllsrc as hsi already reset & pllmul *12  8/2*12=48M
//		RCC->CFGR |= RCC_CFGR_PLLMUL12;
		
		/* Enable PLL */
		RCC->CR |= RCC_CR_PLLON;
		/* Wait till PLL is ready */
		while((RCC->CR & RCC_CR_PLLRDY) == 0);
		
		//select system clock as pll
		RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
		RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
		
		//wait pll use as system clock
		while((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL);
 
		//Set ADC prescaler /4  12M
	//	RCC->CFGR |= RCC_ADCCLK_PCLK_Div4;
		//Set ADC clock source
		RCC_ADCCLKConfig(RCC_ADCCLK_PCLK_Div4);
		//Set usart clock source
		RCC_USARTCLKConfig(RCC_USART1CLK_PCLK);
		//Set IIC clock source
		RCC_I2CCLKConfig(RCC_I2C1CLK_SYSCLK);	
		
  }
	#endif /* PLL_SOURCE_HSI */

//————————————————
//版权声明：本文为CSDN博主「xia_xia_mg」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
//原文链接：https://blog.csdn.net/xia_xia_mg/article/details/118764159

	#if 0 
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
  
  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
  /* Enable HSE */    
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 
  /* Wait till HSE is ready and if Time out is reached exit */
  do
  {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
    StartUpCounter++;  
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));

  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
  {
    HSEStatus = (uint32_t)0x01;
  }
  else
  {
    HSEStatus = (uint32_t)0x00;
  }  

  if (HSEStatus == (uint32_t)0x01)
  {
    /* Enable Prefetch Buffer and set Flash Latency */
    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
 
    /* HCLK = SYSCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
      
    /* PCLK = HCLK */
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;

    /* PLL configuration = HSE * 6 = 48 MHz */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
            
    /* Enable PLL */
    RCC->CR |= RCC_CR_PLLON;

    /* Wait till PLL is ready */
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
    {
    }

    /* Select PLL as system clock source */
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    

    /* Wait till PLL is used as system clock source */
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
    {
    }
  }
  else
  { /* If HSE fails to start-up, the application will have wrong clock 
         configuration. User can add here some code to deal with this error */
  }
#endif  
}

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