采用LT9211芯片实现;
其中驱动加速
//DTS
#if (lt9211_face==1)
#include "screen-timing/panel-lt9211-1920x1080.dtsi"
#elif (lt9211_face==2)
#include "screen-timing/panel-lt9211-1366x768.dtsi"
#elif (lt9211_face==3)
#include "screen-timing/panel-lt9211-1280x800.dtsi"
#elif (lt9211_face==4)
#include "screen-timing/panel-lt9211-800x1280.dtsi"
#elif (lt9211_face==5)
#include "screen-timing/panel-lt9211-1024x600.dtsi"
#elif (lt9211_face==6)
#include "screen-timing/panel-lt9211-1280x1024.dtsi"
#endif
lt8912 {
compatible = "lontium,lt8912";
reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
bl_en-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
lcd_en-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
lt9211-face = <lt9211_face>;
lt9211-jeida = <0>;
lt9211-bit6 = <0>;
i2c-bus = <&i2c4>;
};
backlight_lvds: backlight-lvds {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&bl_pwren>;
regulator-name = "lvdsbl_pwren";
regulator-always-on;
regulator-boot-on;
};
下面试驱动文件
\sdk\kernel\drivers\gpu\drm\bridge\lt8912.c
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018 Rockchip Electronics Co. Ltd.
*/
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_graph.h>
#include <linux/regmap.h>
#ifdef CONFIG_OF
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#endif
#include <dt-bindings/gpio/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "lt9211.h"
struct lt8912 {
struct device *dev;
struct regmap *regmap;
struct gpio_desc *reset_n;
struct gpio_desc *enable_n;
struct gpio_desc *bl_en;
struct gpio_desc *lcd_en;
int lcd_face;
int jeida;
int bit6;
};
u16 hact, vact;
u16 hs, vs;
u16 hbp, vbp;
u16 htotal, vtotal;
u16 hfp, vfp;
u8 VideoFormat=0;
enum VideoFormat Video_Format;
#define MIPI_LANE_CNT MIPI_4_LANE // 0: 4lane
#define MIPI_SETTLE_VALUE 0x0A //0x05 0x0a
#define PCR_M_VALUE 0x17 //0x14 , for display quality
//Video_pattern
#define VIDEO_PATTERN 1 //ENABLE or DISABLE
// //hfp, hs, hbp,hact,htotal,vfp, vs, vbp, vact,vtotal,
struct video_timing video_640x400_60Hz ={ 96, 64, 58, 640, 858, 87, 6, 32, 400, 525, 27000};//yelsin add for WYZN
struct video_timing video_640x480_60Hz ={ 8, 96, 40, 640, 800, 33, 2, 10, 480, 525, 25000};
struct video_timing video_720x480_60Hz ={16, 62, 60, 720, 858, 9, 6, 30, 480, 525, 27000};
struct video_timing video_1024x600_60Hz = {100, 20, 180,1024, 1324, 12, 3, 20, 600, 635 , 55000};
struct video_timing video_1280x720_60Hz ={110,40, 220,1280, 1650, 5, 5, 20, 720, 750, 74250};
struct video_timing video_1280x720_30Hz = {110,40, 220,1280, 1650, 5, 5, 20, 720, 750, 37125};
struct video_timing video_1366x768_60Hz ={10, 100,60,1366, 1536, 30, 5, 10, 768, 813, 74250};
struct video_timing video_1280x1024_60Hz ={48,112,248,1280, 1688, 5, 5, 32, 1024, 1066, 108000};
struct video_timing video_1920x1080_25Hz = {88, 44, 148,1920, 2200, 4, 5, 36, 1080, 1125, 74250};
struct video_timing video_1920x1080_30Hz ={88, 44, 148,1920, 2200, 4, 5, 36, 1080, 1125, 74250};
//struct video_timing video_1920x1080_60Hz ={48, 1, 128,1920, 2089, 6, 1, 33, 1080, 1120, 145000};
struct video_timing video_1920x1080_60Hz ={160, 20, 120,1920, 2220, 15, 10, 25, 1080, 1130, 148500};//orgxunde
struct video_timing video_3840x1080_60Hz ={176,88, 296,3840, 4400, 4, 5, 36, 1080, 1125, 297000};
struct video_timing video_1920x1200_60Hz ={48, 32, 80,1920, 2080, 3, 6, 26, 1200, 1235, 154000};
struct video_timing video_3840x2160_30Hz ={176,88, 296,3840, 4400, 8, 10, 72, 2160, 2250, 297000};
struct video_timing video_3840x2160_60Hz ={176,88, 296,3840, 4400, 8, 10, 72, 2160, 2250, 594000};
struct video_timing video_1920x720_60Hz ={148, 44, 88,1920, 2200, 28, 5, 12, 720, 765, 88000}; //fromWANGYONGinc
struct video_timing video_1280x800_60Hz ={60,10, 100,1280, 1450, 20, 5, 20, 800, 845, 66000};
struct video_timing video_800x1280_60Hz ={72,24, 24,800, 920, 12, 2, 10, 1280, 1304, 72000};
static void lt8912_power_on(struct lt8912 *lt8912);
/****************************************************************
* funtion: Desscpll ????£?ó?óúPCR ???′Pixel Clock ?£
******************************************************************/
void LT9211_DesscPll_mipi(struct lt8912 *lt8912,struct video_timing *video_format)
{
u32 pclk;
unsigned int pll_lock_flag;
u8 i;
u8 pll_post_div;
u8 pcr_m;
pclk = video_format->pclk_khz;
printk("\r\n LT9211_DesscPll: set rx pll = %ld", pclk);
regmap_write(lt8912->regmap,0xff,0x82);
regmap_write(lt8912->regmap,0x2d,0x48);
if(pclk > 80000)
{
regmap_write(lt8912->regmap,0x35,0x81);
pll_post_div = 0x01;
}
else if(pclk > 20000)
{
regmap_write(lt8912->regmap,0x35,0x82);
pll_post_div = 0x02;
}
else
{
regmap_write(lt8912->regmap,0x35,0x83);
pll_post_div = 0x04;
}
pcr_m = (u8)((pclk*4*pll_post_div)/25000);
printk("\r\n LT9211_DesscPll: set rx pll pcr_m = 0x%bx", pcr_m);
regmap_write(lt8912->regmap,0xff,0xd0);
regmap_write(lt8912->regmap,0x2d,0x40); //M_up_limit
regmap_write(lt8912->regmap,0x31,0x10); //M_low_limit
regmap_write(lt8912->regmap,0x26,pcr_m|0x80);
regmap_write(lt8912->regmap,0xff,0x81); //dessc pll sw rst
regmap_write(lt8912->regmap,0x20,0xef);
regmap_write(lt8912->regmap,0x20,0xff);
#if 1
/* pll lock status */
for(i = 0; i < 1 ; i++)
{
regmap_write(lt8912->regmap,0xff,0x81);
regmap_write(lt8912->regmap,0x11,0xfb); /* pll lock logic reset */
regmap_write(lt8912->regmap,0x11,0xff);
regmap_write(lt8912->regmap,0xff,0x87);
//pll_lock_flag = HDMI_ReadI2C_Byte(0x04);
regmap_read(lt8912->regmap, 0x04, &pll_lock_flag);
if(pll_lock_flag & 0x01)
{
printk("\r\n LT9211_DesscPll: dessc pll locked");
}
else
{
regmap_write(lt8912->regmap,0xff,0x81); //dessc pll sw rst
regmap_write(lt8912->regmap,0x20,0xef);
regmap_write(lt8912->regmap,0x20,0xff);
printk("\r\n LT9211_DesscPll: dessc pll unlocked,sw reset");
}
}
#endif
}
void LT9211_MipiPcr(struct lt8912 *lt8912)
{
u8 loopx;
unsigned int pcr_m;
unsigned int r1;
regmap_write(lt8912->regmap,0xff,0xd0);
if(lt8912->lcd_face==LVDS1280x1024||lt8912->lcd_face==LVDS1024x600){
regmap_write(lt8912->regmap,0x0c,0x20); //fifo position
regmap_write(lt8912->regmap,0x1c,0x20); //fifo position
}
else {
regmap_write(lt8912->regmap,0x0c,0x60); //fifo position
regmap_write(lt8912->regmap,0x1c,0x60); //fifo position
}
regmap_write(lt8912->regmap,0x24,0x70); //pcr mode( de hs vs)
regmap_write(lt8912->regmap,0x2d,0x30); //M up limit
regmap_write(lt8912->regmap,0x31,0x0a); //M down limit
/*stage1 hs mode*/
regmap_write(lt8912->regmap,0x25,0xf0); //line limit
regmap_wri