Xilinx FPGA:vivado实现流水灯、翻转灯结合按键消抖的设计，采用block块的方式

一、要求

采用模块化设计完成：

1、按下key_0的时候进行流水灯，并完成key_0的按键消抖

2、按下key_1的时候进行翻转灯，并完成key_1的按键消抖

二、分析

三、代码设计

（1）控制流水灯的按键进行消抖的模块

`timescale 1ns / 1ps
module key_water_led(
input                sys_clk       ,
input                rst_n         ,
input    wire        key          ,
output   wire        key_flag_1     
    );

  parameter                TIME_20ms=20'd50_000_0      ; //定义消抖计时器最大值   
  reg      [20:0]          count_20ms_1          ;//按键1计时器
 
always@(posedge  sys_clk)
     if( !rst_n )
         count_20ms_1 <= 0 ;
         else if ( key==0 )begin
              if ( count_20ms_1 == TIME_20ms-1 )
                 count_20ms_1 <= count_20ms_1 ;
              else
                 count_20ms_1 <= count_20ms_1+1 ;         
         end      
         else
         count_20ms_1<= 0 ;

assign  key_flag_1=(count_20ms_1 == TIME_20ms-2)?1:0;

endmodule

（2）控制翻转灯的按键进行消抖的模块

`timescale 1ns / 1ps
module key_jump_led(
input                sys_clk       ,
input                rst_n         ,
input    wire    key          ,
output   wire        key_flag_2     
    );

  parameter                TIME_20ms=20'd50_000_0      ; //定义消抖计时器最大值   
  reg      [20:0]           count_20ms_2          ;//按键1计时器
 
always@(posedge  sys_clk)
     if( !rst_n )
          count_20ms_2<= 0 ;
         else if ( key==0 )begin
              if (  count_20ms_2 == TIME_20ms-1 )
                  count_20ms_2 <=  count_20ms_2;
              else
                  count_20ms_2 <=  count_20ms_2+1 ;         
         end      
         else
          count_20ms_2<= 0 ;

assign  key_flag_2=(count_20ms_2 == TIME_20ms-2)?1:0;

endmodule

（3）流水灯模块

`timescale 1ns / 1ps

module water_led(
input                sys_clk       ,
input                rst_n         ,
output  reg[3:0]     water_led     
    );
    
parameter         TIME_1s=26'd50_000_000     ;//定义流水灯计时器\翻转灯计时器最大值
 reg      [26:0]          count_1s    ;
//流水灯和翻转灯的1s计时器

always@(posedge sys_clk)
      if(!rst_n)
      count_1s <= 0   ;
      else if(count_1s == TIME_1s-1 )
      count_1s <= 0   ;
      else
      count_1s <= count_1s+1;
      
always@(posedge  sys_clk)
      if(!rst_n)
        water_led <= 4'b0001 ;
      else if(  count_1s == TIME_1s-1 )
        water_led <={water_led[0],water_led[3:1]} ;
      else 
        water_led<=water_led;

endmodule

（4）翻转灯模块

`timescale 1ns / 1ps

module jump_led(
input                sys_clk       ,
input                rst_n         ,
output  reg[3:0]     jump_led    
    );
    
parameter         TIME_1s=26'd50_000_000     ;//定义流水灯计时器\翻转灯计时器最大值
 reg      [26:0]          count_1s    ;
//流水灯和翻转灯的1s计时器

always@(posedge sys_clk)
      if(!rst_n)
      count_1s <= 0   ;
      else if(count_1s == TIME_1s-1 )
      count_1s <= 0   ;
      else
      count_1s <= count_1s+1;
      
always@(posedge sys_clk)
      if(!rst_n)
        jump_led <= 4'b0101   ;
      else if(  count_1s == TIME_1s-1)
        jump_led<= ~jump_led    ;
      else
        jump_led <= jump_led    ;

endmodule

（5）顶层控制模块

`timescale 1ns / 1ps
module CTRL(
    input       sys_clk          ,
    input       rst_n           ,
    input       key_flag_1       ,
    input       key_flag_2       ,
    input   [3:0] water_led     ,
    input   [3:0] jump_led      ,
    output  reg [3:0]   led
    );
reg     en1         ;
reg     en2         ;
always@(posedge sys_clk)
    if(!rst_n)
        en1 <= 0;
    else if(key_flag_1)
        en1 <= 1;    长信号
    else if(key_flag_2)
        en1 <= 0;
    else
        en1 <= en1;
always@(posedge sys_clk)
    if(!rst_n)
        en2 <= 0;
    else if(key_flag_2)
        en2 <= 1;
    else if(key_flag_1)
        en2 <= 0;
    else
        en2 <= en2;
always@(posedge sys_clk)
    if(!rst_n)
        led <= 4'b1111;
    else if(en1)   
        led <= water_led;   ///0001   0010  0100  1000
    else if(en2)
        led <= jump_led;
    else
        led <= led;

endmodule

四、用block块进行模块拼接

生成.v文件：

​
//Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2020.1 (win64) Build 2902540 Wed May 27 19:54:49 MDT 2020
//Date        : Wed Jun  5 10:39:30 2024
//Host        : LAPTOP-A2IQ2GRP running 64-bit major release  (build 9200)
//Command     : generate_target led_wrapper.bd
//Design      : led_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module led_wrapper
   (key_0,
    key_1,
    led_0,
    rst_n_0,
    sys_clk_0);
  input key_0;
  input key_1;
  output [3:0]led_0;
  input rst_n_0;
  input sys_clk_0;

  wire key_0;
  wire key_1;
  wire [3:0]led_0;
  wire rst_n_0;
  wire sys_clk_0;

  led led_i
       (.key_0(key_0),
        .key_1(key_1),
        .led_0(led_0),
        .rst_n_0(rst_n_0),
        .sys_clk_0(sys_clk_0));
endmodule

​