Xilinx FPGA:vivado实现秒表

项目要求：后两位到59的时候给前2位进1

TOP模块：

`timescale 1ns / 1ps
module top(
    input                        sys_clk  ,
    input                        rst_n    ,
    output     wire[3:0]         DIG      ,
    output     wire[7:0]         SEG     

    );
   
    parameter         TIME_1s = 26'd50_000_000 ;
    parameter         number_max = 16'd59_59     ;
    
    reg  [13:0]        number   ;
    reg  [25:0]        cnt_1s;//_1s   ; 
    
    //例化数码管状态机模块
    timer_tude    u2(
                 .  sys_clk(sys_clk)   ,
                 .  rst_n  (rst_n  )   ,
                 .  number (number )   ,
                 .   DIG   ( DIG   )   ,
                 .   SEG   ( SEG   )
    );
    
//    /数码管计时器
//always@(posedge sys_clk)
//    if(!rst_n)begin
//        cnt <= 0;
//        number <= 0;
//    end
//    else if(cnt == TIME_1s - 1)begin
//        cnt <= 0;
//        if(number == 16'd9999) 
//            number <= 0;
//        else
//            number <= number + 1;   
//    end
//    else begin
//        number <= number;
//        cnt <= cnt + 1;
//    end
    
    ///计数器
    always@(posedge sys_clk)
          if(!rst_n)
          number <= 0 ;
          else if ( cnt_1s == TIME_1s -1 && number == number_max)
          number <= 0 ;
          else if(cnt_1s == TIME_1s -1 && number%100 == 16'd59)
          number <= number + 16'd41  ;
          else if ( cnt_1s == TIME_1s -1 )
          number <= number +1 ;
          else
          number = number     ;
    
    ///数码管计时器   1s增加一个数字
    always@(posedge sys_clk)
          if (!rst_n)
          cnt_1s <= 0 ;
          else if ( cnt_1s == TIME_1s -1)
          cnt_1s <= 0 ;
          else
          cnt_1s <= cnt_1s +1 ;
    
    
    
    
    
    
    
endmodule

数码管状态机模块：

`timescale 1ns / 1ps
module timer_tude(
    input                      sys_clk   ,
    input                      rst_n     ,
    input      wire[13:0]      number    ,
    output     wire[3:0]        DIG     ,
    output     wire[7:0]        SEG  
    );
    parameter                MODE = 0         ;
    
    reg[3:0]                    dig              ;
    wire[7:0]                   seg_out          ;
    reg[3:0]                    num              ;
    
    //数据处理
    wire[3:0]                 num_ge            ;
    wire[3:0]                 num_shi           ;
    wire[3:0]                 num_bai           ;
    wire[3:0]                 num_qian          ;
    
    assign     num_ge   = number%10         ; 
    assign     num_shi  = number/10%10         ; 
    assign     num_bai  = number/100%10         ; 
    assign     num_qian = number/1000%10         ; 
    
    //状态机
    reg[3:0]                  cur_state        ;
    reg[3:0]                  next_state       ; 
    reg[15:0]                 cnt_1ms           ;
    
    parameter                TIME_1ms = 16'd50_000 ; 
    
    localparam                 IDLE = 4'b0000   ;
    localparam                 GE   = 4'b0001   ;
    localparam                 SHI  = 4'b0010   ;
    localparam                 BAI  = 4'b0100   ;
    localparam                 QIAN = 4'b1000   ;
    
    
    always@(posedge sys_clk)
          if(!rst_n)
             cur_state <= IDLE   ;
             else
             cur_state <= next_state ;
             
    always@(*)
          case(cur_state)
          IDLE  :
                 begin
                 next_state = GE ;                
                 end
          GE    :
                 begin
                 if( cnt_1ms == TIME_1ms -1)
                 next_state <= SHI  ;
                 else
                 next_state <= cur_state ;
                 end
          SHI   : 
                 begin
                 if( cnt_1ms == TIME_1ms -1)
                 next_state <= BAI  ;
                 else
                 next_state <= cur_state ;
                 end
          BAI   :
                 begin
                 if( cnt_1ms == TIME_1ms -1)
                 next_state <= QIAN  ;
                 else
                 next_state <= cur_state ;
                 end
          QIAN  :
                 begin
                 if( cnt_1ms == TIME_1ms -1)
                 next_state <= GE  ;
                 else
                 next_state <= cur_state ;
                 end
      endcase
      
     always@(posedge sys_clk)
          if(!rst_n)begin
             cnt_1ms <= 0 ;
             dig     <= 0 ;
             num     <= 0 ;
             end
          else
          case(cur_state)
          IDLE  :
                 begin
                  cnt_1ms <= 0 ;
                  dig     <= 0 ;
                  num     <= 0 ;                
                 end
          GE    : 
                 begin                       
                 dig <= 4'b1110 ;            
                 num <= num_ge  ;            
                 if( cnt_1ms == TIME_1ms -1 )
                 cnt_1ms <= 0 ;              
                 else                        
                 cnt_1ms <= cnt_1ms +1 ;     
                 end                           
          SHI   :
                 begin                       
                 dig <= 4'b1101 ;            
                 num <= num_shi  ;            
                 if( cnt_1ms == TIME_1ms -1 )
                 cnt_1ms <= 0 ;              
                 else                        
                 cnt_1ms <= cnt_1ms +1 ;     
                 end 
          BAI   :
                  begin                       
                 dig <= 4'b1011 ;            
                 num <= num_bai  ;            
                 if( cnt_1ms == TIME_1ms -1 )
                 cnt_1ms <= 0 ;              
                 else                        
                 cnt_1ms <= cnt_1ms +1 ;     
                 end 
          QIAN  :
                  begin                       
                 dig <= 4'b0111 ;            
                 num <= num_qian  ;            
                 if( cnt_1ms == TIME_1ms -1 )
                 cnt_1ms <= 0 ;              
                 else                        
                 cnt_1ms <= cnt_1ms +1 ;     
                 end 
                 default:;
     endcase
     //例化解码器
decoder  u1(
.  num     ( num   ) ,
. seg_out  (seg_out)

    );
     
      assign      DIG = (MODE == 0) ? dig : ~dig           ; 
      assign      SEG = (MODE == 0) ? seg_out : ~seg_out   ; 
     
endmodule

译码器模块：

`timescale 1ns / 1ps
module decoder(
input     [3:0]      num  ,
output    reg[7:0]  seg_out  

    );
    always@(*)
       case(num)
       4'd0: seg_out = 8'h3f;
       4'd1: seg_out = 8'h06;
       4'd2: seg_out = 8'h5b;
       4'd3: seg_out = 8'h4f;
       4'd4: seg_out = 8'h66;
       4'd5: seg_out = 8'h6d;
       4'd6: seg_out = 8'h7d;
       4'd7: seg_out = 8'h07;
       4'd8: seg_out = 8'h7f;
       4'd9: seg_out = 8'h6f;
       default:;  
       endcase       
    
endmodule