STM32F0使用内部晶振

最新推荐文章于 2024-09-11 20:49:02 发布

luoshunluobo

最新推荐文章于 2024-09-11 20:49:02 发布

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文章标签： stm32

原文链接：https://www.cnblogs.com/beiyhs/p/11211691.html

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STM32F051使用内部晶振（48M）并可使PF1用作普通IO口，实测可行，用如下代码替换库中时钟配置就可以

static void SetSysClock(void)
{
__IO uint32_t StartUpCounter = 0, HSIStatus = 0;

   RCC->CR &= ~((uint32_t)RCC_CR_HSEON); //关闭外部时钟
   RCC->CR |= ((uint32_t)RCC_CR_HSION); //使能内部时钟 HSI
   do //等待内部时钟起振
   {
       HSIStatus = RCC->CR & RCC_CR_HSIRDY; // 设置RCC
       StartUpCounter++;         //启动计数器
   }
   while((HSIStatus== 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));             // 等待 HSE 启动稳定

   if((RCC->CR & RCC_CR_HSIRDY) != RESET)    //判断启动状态
   {
       HSIStatus = (uint32_t)0x01;
   }
   else
   {
       HSIStatus = (uint32_t)0x00; //启动不成功
   }

   if(HSIStatus == (uint32_t)0x01) //启动成功
   {
       /* Enable Prefetch Buffer and set Flash Latency */
       FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; //flash总线时钟使能

/* HCLK = SYSCLK */ //AHB总线时钟HCLK（是系统时钟SYSCLK经过AHB分频器分频后得到的时钟，

//一般设置1分频，HCLK=SYSSCLK=48MHz；

RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; //AHB总线时钟 HCLK = SYSCLK/1=48MHz

/* PCLK = HCLK */ //APB总线时钟PCLK等于AHB总线时钟/1 PCLK=HCLK/1
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; // PCLK=HCLK/1=48M/1=48M

       /* PLL configuration = HSI/2 * 12= 48 MHz */
       RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL));
       RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL12);

                                                                                                                                                   //RC时钟2分频后进行12倍频
                                                                                                                                                   //=8M/2*12=48M
       RCC->CR |= RCC_CR_PLLON;    //使能锁相环倍频开关 /* Enable PLL */

while((RCC->CR & RCC_CR_PLLRDY) == 0) //等待锁相环就绪
{ }

       /* Select PLL as system clock source */ //选择锁相环输出时钟作为系统时钟
       RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
       RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;

       while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
       { } //等待锁相环输出时钟已经成为系统时钟
   }
   else
   { }
}