pc_rom代码及其仿真

module inst_fetch(input wire clk,input wire rst,output wire[31:0] inst_o);
wire[5:0] pc;wire rom_ce;
pc_reg pc_reg0(.clk(clk),.rst(rst),.ce(rom_ce),.pc(pc));
rom rom0(.addr(pc),.ce(rom_ce),.inst(inst_o));
endmodule 
module pc_reg(               input wire rst,               input wire clk,               output reg[5:0] pc,               output reg ce);
always @(posedge clk)begin   if (rst==1'b1)   begin   ce<=1'b0;   end   else   begin   ce<=1'b1;   endend
always @(posedge clk)begin    if (ce==1'b0)    begin     pc<=6'h00;    end    else    begin    pc<=pc+1'b1;    endend 
endmodule 
module rom(input wire[5:0] addr,input wire ce,output reg[31:0] inst);
reg[31:0] rom[63:0];
initial $readmemh ("D:/chengxu/yingjian/pc_rom/rom.data",rom);
always @(*)begin    if (ce == 1'b0)    begin    inst <= 32'h0;    end    else    begin    inst<= rom[addr];    endend
endmodule 
module inst_fetch_tb;
reg CLOCK;reg rst;wire[31:0] inst;
initialbeginCLOCK = 1'b0;forever #10 CLOCK =~CLOCK;end
initial begin rst =1'b1;#195 rst =1'b0;#1000 $stop;end
inst_fetch inst_fetch0(.clk(CLOCK),.rst(rst),.inst_o(inst));
endmodule