【无标题】华硕tinkerboard 2s uboot下网络及emmc问题

1、uboot源码下载：
    https://github.com/TinkerBoard2/u-boot

    tinkerboard 2s相关资料汇总：
    https://smartfire.cn/forum.php?mod=viewthread&tid=5240&highlight=tinker%2Bboard%2Bs
    
2、uboot下tftp 网络不通

原因为网络GMAC的时钟由CPU提供，dts配置按照输入配置，其次时钟频率配置并非125M，具体修改如下：
    

diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts
index 7bb0688..abc2748 100644
--- a/arch/arm/dts/rk3399-evb.dts
+++ b/arch/arm/dts/rk3399-evb.dts
@@ -364,18 +364,19 @@
 };
 
 &gmac {
-        phy-supply = <&vcc_phy>;
+        phy-supply = <&vcc3v3_sys>;
        phy-mode = "rgmii";
-       clock_in_out = "input";
+       clock_in_out = "output";
+       assigned-clock-rates = <125000000>;
        snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
        snps,reset-active-low;
        snps,reset-delays-us = <0 10000 50000>;
        assigned-clocks = <&cru SCLK_RMII_SRC>;
-       assigned-clock-parents = <&clkin_gmac>;
+       assigned-clock-parents = <&cru SCLK_MAC>;
        pinctrl-names = "default";
        pinctrl-0 = <&rgmii_pins>;
-       tx_delay = <0x28>;
-       rx_delay = <0x11>;
+       tx_delay = <0x25>;
+       rx_delay = <0x20>;
        status = "okay";
 };
 
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
index 55d09af..4d60bc5 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h
@@ -81,7 +81,7 @@ check_member(rk3399_cru, sdio1_con[1], 0x594);
 #define APLL_HZ                (600*MHz)
 #define GPLL_HZ                (800 * MHz)
 #define CPLL_HZ                (384*MHz)
-#define NPLL_HZ                (600 * MHz)
+#define NPLL_HZ                (625 * MHz)
 #define PPLL_HZ                (676*MHz)
 
 #define PMU_PCLK_HZ    (48*MHz)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 3e59105..a78ee1d 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -722,7 +722,7 @@ config ROCKCHIP_VENDOR_PARTITION
 config USING_KERNEL_DTB
        bool "Using dtb from Kernel/resource for U-Boot"
        depends on RKIMG_BOOTLOADER && OF_LIVE
-       default y
+       default n
        help
          This enable support to read dtb from resource and use it for U-Boot,
          the uart and emmc will still using U-Boot dtb, but other devices like
          
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index cce0b48..284c96c 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -171,6 +171,15 @@ enum {
        ACLK_PERIHP_DIV_CON_SHIFT       = 0,
        ACLK_PERIHP_DIV_CON_MASK        = 0x1f,
 
+       /* CLKSEL_CON20 */
+       GMAC_PLL_SHIFT        = 14,
+       GMAC_PLL_MASK                   = 0x3,
+       GMAC_PLL_SELECT_CPLL            = 0x0,
+       GMAC_PLL_SELECT_GPLL            = 0x1,
+       GMAC_PLL_SELECT_NPLL            = 0x2,
+       GMAC_DIV_CON_MASK               = GENMASK(12, 8),
+       GMAC_DIV_CON_SHIFT              = 0x8,
+
        /* CLKSEL_CON21 */
        ACLK_EMMC_PLL_SEL_SHIFT         = 7,
        ACLK_EMMC_PLL_SEL_MASK          = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
@@ -897,8 +906,47 @@ static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
                 * Implement this once it becomes necessary and print an error
                 * if someone tries to use it (while it remains unimplemented).
                 */
-               pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
-               ret = 0;
+               pr_err("go %s: internal clock is UNIMPLEMENTED\n", __func__);
+
+
+               u32 con = readl(&cru->clksel_con[20]);
+                ulong pll_rate;
+                u8 div;
+
+                if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+                    GMAC_PLL_SELECT_CPLL){
+                       printf("zeng CPLL\n");
+                        pll_rate = CPLL_HZ;
+               }
+                else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+                         GMAC_PLL_SELECT_GPLL){
+                       printf("zeng GPLL\n");
+                        pll_rate = GPLL_HZ;
+               }
+                else if (((con >> GMAC_PLL_SHIFT) & GMAC_PLL_MASK) ==
+                         GMAC_PLL_SELECT_NPLL){
+                       printf("zeng NPLL\n");
+                          pll_rate = NPLL_HZ;
+               }
+               else if (((con >> GMAC_PLL_SHIFT) & 0x3) ==
+                               GMAC_PLL_SELECT_NPLL){
+                       printf("zeng NPLL\n");
+                       pll_rate = NPLL_HZ;
+               }
+                else /* CPLL is not set */{
+                       printf("zeng error!\n");
+                        return -EPERM;
+               }
+
+                div = DIV_ROUND_UP(pll_rate, rate) - 1;
+               printf("zeng:div=%x\n",div);
+                if (div <= 0x1f)
+                        rk_clrsetreg(&cru->clksel_con[20], GMAC_DIV_CON_MASK,
+                                     div << GMAC_DIV_CON_SHIFT);
+                else
+                        debug("Unsupported div for gmac:%d\n", div);
+
+                return DIV_TO_RATE(pll_rate, div);
        }
 
        return ret;
@@ -1002,6 +1050,7 @@ static ulong rk3399_tsadc_set_clk(struct rk3399_cru *cru, uint hz)
        return rk3399_tsadc_get_clk(cru);
 }

3、uboot下mmc命令写emmc报错：

Writing to MMC(0)... sdhci_transfer_data: Error detected in status(0x608000)!
MMC error: The cmd index is 25, ret is -70
mmc write failed

原因驱动没有对emmc的phy进行初始化设置，修改如下：

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 378eb97..ceddd00 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -91,6 +91,11 @@ struct sdhci_data {
 
 static int rk3399_emmc_phy_init(struct udevice *dev)
 {
+    struct rockchip_sdhc *priv = dev_get_priv(dev);
+    
+    writel(0xFFFF3B00, &priv->phy->emmcphy_con[0]);
+    writel(0xFFFF03FF, &priv->phy->emmcphy_con[2]);
+    writel(0xFFFF01FF, &priv->phy->emmcphy_con[3]);
        return 0;
 }
 
--