2021-06-01 uvm_guide 6

uvm_user_guide_1.2 @2011-2015
6.6.3.2 Setting Verbosity
The uvm_cmdline_processor looks for the +UVM_VERBOSITY option to change the verbosity for all
UVM components. It is also possible to control the verbosity in a much more granular way by using the
+uvm_set_verbosity option. The +uvm_set_verbosity option has a specific format that allows
control over the phases where the verbosity change applies, and in the case of time-consuming phases,
exactly what time it applies. Typically, verbosity is only turned up during time-consuming phases as the test
approaches the time where an error occurs to help in debugging that error. The simulation will run faster if it
is not burdened by generating debug messages earlier on where they are not required.
The +uvm_set_verbosity option is used as follows.
sim_cmd
+uvm_set_verbosity=component_name,id,verbosity,phase_name,optional_time
In a similar fashion, the severity, and also the action taken, can be modified as follows.
sim_cmd +uvm_set_action=component_name,id,severity,action
sim_cmd +uvm_set_severity=component_name,id,current_severity,new_severity

so example
+uvm_set_verbosity=uvm_test_top.env.ahb_system_env.,ALL,UVM_NONE,run
+uvm_set_verbosity=tb_top.pcie_inst,ALL,UVM_NONE,time,0" 就是设置tb_top下面的pcie_inst的verbosity为UVM_NONE
引申：
uvm_cmdline_processor
https://www.cnblogs.com/jiang-ic/p/10579416.html