求用VHDL语言24进制可逆计数显示译码器

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity led_24 is port(clk,clr,ena:in std_logic; cq10_out,cq2_out:out std_logic_vector(3 downto 0) ); end led_24;architecture behav of led_24 is component led24 port(clk,clr,ena:in std_logic; cnt10,cnt2:out std_logic_vector(3 downto 0)); end component; component decoder_10 port(cq10_1:IN STD_LOGIC_VECTOR(3 DOWNTO 0); cq10_out:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); end component; component decoder_2 port(cq2_1:IN STD_LOGIC_VECTOR(3 DOWNTO 0); cq2_out:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); end component;signal net1,net2:std_logic_vector(3 downto 0); begin u1:led24 port map(clk=>clk,clr=>clr,ena=>ena,cnt10=>net1,cnt2=>net2); u2:decoder_10 port map(cq10_1=>net1,cq10_out=>cq10_out); u3:decoder_2 port map(cq2_1=>net2,cq2_out=>cq2_out);END architecture behav;