求用VHDL语言24进制可逆计数显示译码器
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity led_24 is port(clk,clr,ena:in std_logic; cq10_out,cq2_out:out std_logic_vector(3 downto 0) ); end led_24;architecture behav of led_24 is component led24 port(clk,clr,en
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2020-09-28 21:11:53 ·
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