实验要求:设计一个具有无有效输入标志和非法输入标志输出的16-4编码器,实体名称为“encode_16_4”,其引脚名称和逻辑功能如下表所示。
输入 | 输出 | |||||||||||
in0 | In1 | in2 | in3 | in14 | in15 | dout(3位总线) | nul | inv | ||||
0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | |
1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | |
1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | |
0 | 0 | |||||||||||
1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | |
1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | |
1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | |
其他输入值 | 0 | 0 | 0 | 0 | 0 | 1 |
实验步骤:①建立工程、②编辑代码、③编译及修改错误、④建立仿真波形并仿真、⑤应用HEDL-2实验箱观察实际效果,分析设计是否正确。
library ieee;
use ieee.std_logic_1164.all;
entity encode_16_4 is
port(indata:in std_logic_vector(15 downto 0);
dout : out std_logic_vector(3 downto 0);
nul,inv : out std_logic
);
end entity;
architecture rtl of encode_16_4 is
begin
process(indata) is
begin
if(indata="0111111111111111")then
dout<="0000";nul<='0';inv<='0';
elsif(indata="1011111111111111")then
dout<="0001";nul<='0';inv<='0';
elsif(indata="1101111111111111")then
dout<="0010";nul<='0';inv<='0';
elsif(indata="1110111111111111" )then
dout<="0011";nul<='0';inv<='0';
elsif(indata="1111011111111111" )then
dout<="0100";nul<='0';inv<='0';
elsif(indata="1111101111111111")then
dout<="0101";nul<='0';inv<='0';
elsif(indata="1111110111111111")then
dout<="0110";nul<='0';inv<='0';
elsif(indata="1111111011111111")then
dout<="0111";nul<='0';inv<='0';
elsif(indata="1111111101111111" )then
dout<="1000";nul<='0';inv<='0';
elsif(indata="1111111110111111" )then
dout<="1001";nul<='0';inv<='0';
elsif(indata="1111111111011111" )then
dout<="1010";nul<='0';inv<='0';
elsif(indata="1111111111101111" )then
dout<="1011";nul<='0';inv<='0';
elsif(indata="1111111111110111" )then
dout<="1100";nul<='0';inv<='0';
elsif(indata="1111111111111011" )then
dout<="1101";nul<='0';inv<='0';
elsif(indata="1111111111111101" )then
dout<="1110";nul<='0';inv<='0';
elsif(indata="1111111111111110" )then
dout<="1111";nul<='0';inv<='0';
elsif(indata="1111111111111110") then
dout<="0000";nul<='1';inv<='0';
else
dout<="0000";inv<='1';nul<='0';
end if;
end process;
end rtl;