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原创 System Verilog sv : What is :: ?

::

2022-07-29 11:42:06 157 1

原创 Verilog Keyword

Keywords are predefined nonescaped identifiers that define Verilog language constructs. An escaped identifier shall not be treated as a keyword.

2022-06-07 10:57:00 1421

SystemVerilog reserves the keywords listed below:accept_onaliasalwaysalways_combalways_ffalways_latchandassertassignassumeautomaticbeforebeginbindbinsbinsofbitbreakbufbufif0bufif1bytecasecasexcasezcellchandlecheckerclassclocki

2022-05-27 14:52:37 213

原创 My First Article

Master Xunzi said that，the living place and following friends must be chosen, so that I came here to document my progress and growth.As an IC verification engineer, the skill to use English is significant. That's the reason why I want to write all the co

2022-05-06 18:43:40 213

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原创 System Verilog sv : What is :: ?

原创 Verilog Keyword

原创 SV SystemVerilog Keywords

原创 My First Article

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