VHDL——8—3优先编码器

1.真值表

2.VHDL语言

library ieee;
use ieee.std_logic_1164.all;

entity pe8_3 is
    port(a : in std_logic_vector(0 to 7);
	      y : out std_logic_vector(2 downto 0));
end pe8_3;

architecture behave of pe8_3 is
  begin
  process(a)
    begin
	   if a(7) = '0' then y <= "111";
		elsif a(6) = '0' then y <= "110";
		elsif a(5) = '0' then y <= "101";
		elsif a(4) = '0' then y <= "100";
		elsif a(3) = '0' then y <= "011";
		elsif a(2) = '0' then y <= "010";
		elsif a(1) = '0' then y <= "001";
		else y <= "000";
		end if;
    end process;
  end behave;