1.实验代码:
module barrel(W,S,Y);
input [3:0]W;
input [1:0]S;
output [3:0]Y;
wire [3:0]T;
assign {T,Y} = {W,W} >> S;
endmodule
module parity(X,Y);
input [7:0]X;
output [7:0]Y;
assign Y = {^X[6:0],X[6:0]};
endmodule
2.实验截图:
1.实验代码:
module barrel(W,S,Y);
input [3:0]W;
input [1:0]S;
output [3:0]Y;
wire [3:0]T;
assign {T,Y} = {W,W} >> S;
endmodule
module parity(X,Y);
input [7:0]X;
output [7:0]Y;
assign Y = {^X[6:0],X[6:0]};
endmodule
2.实验截图: