1.实验名称:传播延时
2.实验代码
module Add_full_unit_delay(output c_out,sum,input a,b,c_in);
wire w1,w2,w3;
ADD_half_unit_delay M1(w2,w1,a,b);
ADD_half_unit_delay M2(w3,sum,w1,c_in);
or #1 M3(c_out,w2,w3);
endmodule
module ADD_half_unit_delay (output c_out,sum,input a,b);
xor #1 M1(sum,a,b);
and #1 M2(c_out,a,b);
endmodule
3.实验截图
4.实验视频