关于使用Quartus Ⅱ软件编写Verilog HDL语言程序的常见代码模板与测试文件testbench的代模板总结。

工程文件模板：

module A
(
    input    wire    B,
    input    wire    C,
    ...................
    output   wire    D,
    output   wire    E
  );

//assign {D,E} = B + C;
//always@(*)
  输入输出端口赋值操作模块,赋值语句以分号结尾
/*if({B,C} = 3'b000)
      {D,E} = B + C;
   else if()
   .........
  else
  .........*/
/*case({B,C})
    3'b000:D = 8'b0000_0001;
    3'b001:D = 8'b0000_0010;
    ........................
    default:D = 8'b0000_0001;
  endcase*/

endmodule

测试文件testbench模块代码模板：

`timescale 1ns/1ns
module tb_A();

reg     B;
reg     C;
..........
wire    D;
wire    E;

initial
    begin
        B <= 1'b0;
        C <= 1'b0;
        ..........
    end

always #10 B <= {$random} % 2;
always #10 c <= {$random} % 2;
..............................  

initial
    begin
        $timeformat(-9,0,"ns",6);
        $monitor("@time %t:B = %b,C = %b,D = %b,E =%b",$time,B,C,D,E);
    end
A A_inst
(
    .B(B),
    .C(C),
    ......
    .D(D),
    .E(E)
);

endmodule