HDLBits-Verilog:Conditional ternary operator

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于 2024-12-10 11:23:54 发布

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分类专栏： hdlbits-verilog 文章标签： fpga开发 verilog hdlbits 学习刷题

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Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). Use the conditional operator to make two-way min circuits, then compose a few of them to create a 4-way min circuit. You'll probably want some wire vectors for the intermediate results.

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    wire [7:0] min1,min2;
    assign min1 = a>b ? b:a;
    assign min2 = min1>c ? c:min1;
    assign min = min2>d ? d:min2;

endmodule