1-4路数据分配器VHDL描述

library ieee;
use ieee.std_logic_1164.all;

entity sy2 is
    port(data,enable: in std_logic;        --分别为输入端口和使能端口
	 s : in std_logic_vector(1 downto 0);   --选择信号端口
	 y0,y1,y2,y3:OUT STD_LOGIC);  --输出端口      
end sy2;

architecture behave of sy2 is
begin 
  process(enable,s,data)
  begin	
  
     if enable = '0' then
        y0<='0';y1<='0';y2<='0';y3<='0'; 
	 elsif s = "00" then
	  y0<=data;y1<='0';y2<='0';y3<='0';
	 elsif s = "01" then
		y1<=data;y0<='0';y2<='0';y3<='0';
	 elsif s = "10" then
	   y2<=data;y0<='0';y1<='0';y3<='0';
	 elsif s = "11" then
	  y3<=data;y0<='0';y1<='0';y2<='0';
	 end if;
  end process;
end behave;