跨时钟之数据使能选通道设计

module mux_synchronizer(
 input   wire clka ,
  input   wire clkb , 
  input   wire rst , 
  input   wire [3:0]  data_bus , 
  input   wire data_enable_a   ,
   output  reg data_bus_b 
   );
 reg reg_data_enable_a ; 
 reg data_enable_b_mid ;
 reg data_enable_b ; 
 reg [3:0]   reg1_data_bus_a ; 
 wire [3:0]   data_bus_mux ; 
 //时钟域a下同步本地数据及其有效标志信号，改善时序
 always@(posedge clka or posedge rst) begin
        if(rst) begin
              reg_data_enable_a <= 1'b0 ; 
              reg1_data_bus_a   <= 4'd0 ; 
        end 
        else begin
              reg_data_enable_a <= data_enable_a  ; 
              reg1_data_bus_a   <= data_bus ; 
        end
end 
//将数据有效标志信号同步到b时钟域，两级同步器 
always@(posedge clkb or posedge rst) begin
          if(rst) begin 
                data_enable_b_mid <= 1'b0   ; 
                data_enable_b <= 1'b0; 
           end
           else begin 
                 data_enable_b_mid <= reg_data_enable_a; 
                 data_enable_b <= data_enable_b_mid; 
            end 
end 

assign data_bus_mux = data_enable_b ? reg1_data_bus_a : data_bus_b; 
always@(posedge clkb or posedge rst) begin
         if(rst) begin 
                  data_bus_b <= 4'b0; 
         end 
         else begin
                  data_bus_b <= data_bus_mux;
         end
end 
endmodule